Oscar Garnica

A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems

For the last 30 years, several dynamic memory managers (DMMs) have been proposed. Such DMMs include first fit, best fit, segregated fit and buddy systems. Since the performance, memory usage and energy consumption of each DMM differs, software engineers often face difficult choices in selecting the most suitable approach for their applications. This issue has special impact in the field of portable consumer embedded systems, that must execute a limited amount of multimedia applications (e.g., 3D games, video players, signal processing software, etc.), demanding high performance and extensive memory usage at a low energy consumption. Recently, we have developed a novel methodology based on genetic programming to automatically design custom DMMs, optimizing performance, memory usage and energy consumption. However, although this process is automatic and faster than state-of-the-art optimizations, it demands intensive computation, resulting in a time-consuming process. Thus, parallel processing can be very useful to enable to explore more solutions spending the same time, as well as to implement new algorithms. In this paper we present a novel parallel evolutionary algorithm for DMMs optimization in embedded systems, based on the Discrete Event Specification (DEVS) formalism over a Service Oriented Architecture (SOA) framework. Parallelism significantly improves the performance of the sequential exploration algorithm. On the one hand, when the number of generations are the same in both approaches, our parallel optimization framework is able to reach a speed-up of 86.40x when compared with other state-of-the-art approaches. On the other, it improves the global quality (i.e., level of performance, low memory usage and low energy consumption) of the final DMM obtained in a 36.36% with respect to two well-known general-purpose DMMs and two state-of-the-art optimization methodologies.

Hybrid parallelization of a compact genetic algorithm

Genetic algorithms (GAs) are stochastic optimization heuristics in which searches in solution space are carried out by imitating the population genetics stated in Darwins theory of evolution. We have focused this work on compact genetic algorithms (cGAs), which unlike standard GAs do not manage a population of solutions but only mimics its existence. We study several approaches that can be used to implement parallel cGAs in order to reduce the execution times and to improve the quality of the solutions reached by increasing population sizes. The parallelization models adopted to implement GAs can be classified as: centralized, global, fine grained and coarse grained. For a cGA, only the two first models can be applied. Our approach consists of a hybrid model which combines both centralized and global implementations. The cGA incorporates a local search method and has been applied for solving a graph-partitioning problem for solving the Multi-FPGA systems partitioning and placement.

Dynamic capacity-speed tradeoffs in SMT processor caches

Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeoff. This problem is exacerbated in a Simultaneous Multi-Threaded (SMT) processor where the optimal cache design may vary drastically with the number of running threads and their characteristics. We propose to make this capacity-speed cache tradeoff dynamic within an SMT core. We extend a previously proposed globally asynchronous, locally synchronous (GALS) processor core with multi-threaded support, and implement dynamically resizable instruction and data caches. As the number of threads and their characteristics change, these adaptive caches automatically adjust from small sizes with fast access times to higher capacity configurations. While the former is more performance-optimal when the core runs a single thread, or a dual-thread workload with modest cache requirements, higher capacity caches work best with most multiple thread workloads. The use of a GALS microarchitecture permits the rest of the processor, namely the execution core, to run at full speed irrespective of the cache speeds. This approach yields an overall performance improvement of 24.7% over the best fixed-size caches for dual-thread workloads, and 19.2% for single-threaded applications.

Improving SMT performance: an application of genetic algorithms to configure resizable caches

Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallelism (TLP). Nevertheless a good control strategy is required when resources are shared among different threads, so that throughput is optimized. We study the application of evolutionary algorithms to improve the allocation of configurations on the cache hierarchy over a Simultaneous Multithreading (SMT) processor. In this way, resizable caches have demonstrated their efficiency by adapting their configuration according to workload settings, at runtime. More-over, some methodologies and a number of techniques, such as dynamic resource allocation, have previously been developed to optimize the cache hit behavior, trying to improve global SMT performance. In this paper we propose the use of a Genetic Algorithm (GA) to optimize dynamically reconfigurable cache designs. Given that different workloads feature different characteristics and needs, we apply a Genetic Algorithm (GA) for cache designing, in order to obtain a better dynamic configuration that increases the number of instructions per cycle (IPC). The obtained results show the feasibility of the approach and the potential of GAs for SMT optimization.

Fine-grain asynchronous circuits for low-power high performance DSP implementations

The aim of this paper is to present a new approach to creating low-power high-performance DSP using delay-insensitive asynchronous circuits. To attain this, we pipeline the asynchronous circuit at logic gate level in such a way that every functional unit can be pipelined in many stages, up to as many as half the number of gate levels. Also, we want to integrate this approach with the traditional method to synthesise synchronous circuits. In order to achieve this, we create a new library of gates which satisfy the constraints that asynchronous design requires. Finally, we present the results after building a pipelined multiplier with both synchronous and asynchronous approaches,.

Data Based Prediction of Blood Glucose Concentrations Using Evolutionary Methods

Predicting glucose values on the basis of insulin and food intakes is a difficult task that people with diabetes need to do daily. This is necessary as it is important to maintain glucose levels at appropriate values to avoid not only short-term, but also long-term complications of the illness. Artificial intelligence in general and machine learning techniques in particular have already lead to promising results in modeling and predicting glucose concentrations. In this work, several machine learning techniques are used for the modeling and prediction of glucose concentrations using as inputs the values measured by a continuous monitoring glucose system as well as also previous and estimated future carbohydrate intakes and insulin injections. In particular, we use the following four techniques: genetic programming, random forests, k-nearest neighbors, and grammatical evolution. We propose two new enhanced modeling algorithms for glucose prediction, namely (i) a variant of grammatical evolution which uses an optimized grammar, and (ii) a variant of tree-based genetic programming which uses a three-compartment model for carbohydrate and insulin dynamics. The predictors were trained and tested using data of ten patients from a public hospital in Spain. We analyze our experimental results using the Clarke error grid metric and see that 90% of the forecasts are correct (i.e., Clarke error categories A and B), but still even the best methods produce 5 to 10% of serious errors (category D) and approximately 0.5% of very serious errors (category E). We also propose an enhanced genetic programming algorithm that incorporates a three-compartment model into symbolic regression models to create smoothed time series of the original carbohydrate and insulin time series.

Compilable Phenotypes: Speeding-Up the Evaluation of Glucose Models in Grammatical Evolution

This paper presents a method for accelerating the evaluation of individuals in Grammatical Evolution. The method is applied for identification and modeling problems, where, in order to obtain the fitness value of one individual, we need to compute a mathematical expression for different time events. We propose to evaluate all necessary values of each individual using only one mathematical Java code. For this purpose we take profit of the flexibility of grammars, which allows us to generate Java compilable expressions. We test the methodology with a real problem: modeling glucose level on diabetic patients. Experiments confirms that our approach (compilable phenotypes) can get up to 300x reductions in execution time.

Clarke and parkes error grid analysis of diabetic glucose models obtained with evolutionary computation

Diabetes mellitus is a disease that affects to hundreds of millions of people worldwide. Maintaining a good control of the disease is critical to avoid severe long-term complications. In recent years, a lot of research has been made to improve the quality of life of the diabetic patient, especially in the automation of glucose level control. One of the main problems that arises in the (semi) automatic control of diabetes, is to obtain a model that explains the behavior of blood glucose levels with insulin, food intakes and other external factors, fitting the characteristics of each individual or patient. Recently, Grammatical Evolution (GE), has been proposed to solve this lack of models. A proposal based on GE was able to obtain customized models of five in-silico patient data with a mean percentage average error of 13.69%, modeling well also both hyper and hypoglycemic situations. In this paper we have extended the study of Error Grid Analysis (EGA) to prediction models in up to 8 in-silico patients. EGA is commonly used in Endocrinology to test the clinical significance of differences between measurements and real value of blood glucose, but has not been used before as a metric in obtention of glycemia models.

Solving discrete deceptive problems with EMMRS

This paper presents a new method for solving discrete deceptive problems using a genotype to phenotype mapping where a new replacement and shift operator is applied. The method is evaluated using different deceptive problems. Experimental results show how our method obtains a speed-up of 94% with respect to other approaches.

Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution

Technology scaling has offered advantages to embedded systems, such as increased performance, more available memory and reduced energy consumption. However, scaling also brings a number of problems like reliability degradation mechanisms. The intensive activity of devices and high operating temperatures are key factors for reliability degradation in latest technology nodes. Focusing on embedded systems, the memory is prone to suffer reliability problems due to the intensive use of dynamic memory on wireless and multimedia applications. In this work we present a new approach to automatically design dynamic memory managers considering reliability, and improving performance, memory footprint and energy consumption. Our approach, based on Grammatical Evolution, obtains a maximum improvement of 39% in execution time, 38% in memory usage and 50% in energy consumption over state-of-the-art dynamic memory managers for several real-life applications. In addition, the resulting distributions of memory accesses improve reliability. To the best of our knowledge, this is the first proposal for automatic dynamic memory manager design that considers reliability.