Juan P. Oliver

Clock gating and clock enable for FPGA power reduction

This paper presents experimental measurements of power consumption using different techniques to turn off part of a system and switch between active and standby modes. The main ideas analyzed are: clock gating, clock enable, and blocking inputs. The laboratory work is described, including the measurement setups and the benchmark circuits. Quantitative measurements in both a 65 nm CMOS Cyclone III and a 45 nm CMOS Spartan 6 FPGAs are presented. The selected circuits used as benchmarks are different type of multipliers. Results of power consumption in active and standby modes are presented and compared.

Power estimations vs. power measurements in Cyclone III devices

This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers implemented in LUTs and in embedded blocks both with or without pipelining stages. Three type of results are presented: first, the error between power measurements and power estimations; second, the power savings by using pipeline stages, and third, the quantification of power savings by using embedded blocks.

Self-Reconfigurable Constant Multiplier for FPGA

Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and then, its value changes to adapt to new circumstances. In this article, we present a self-reconfigurable constant multiplier suitable for LUT-based FPGAs able to reload the constant in runtime. The pipelined architecture presented is easily scalable to any multiplicand and constant sizes, for unsigned and signed representations. It can be reprogrammed in 16 clock cycles, equivalent to less than 100 ns in current FPGAs. This value is significantly smaller than FPGA partial configuration times. The presented approach is more efficient in terms of area and speed when compared to generic multipliers, achieving up to 91% area reduction and up to 102% speed improvement for the case-study circuits tested. The power consumption of the proposed multipliers are in the range of those of slice-based multipliers provided by the vendor.

Tracking the pipelining-power rule along the FPGA technical literature

This work reviews the contributions of power-oriented pipelining over the last two decades, and adds up-to-date results on 65 nm and 45 nm FPGAs. The data show that power consumption can be reduced by a factor between 0.1 and 0.8 using different levels of pipelining. More than 34 experiments, developed in 12 laboratories in 8 countries during 17 years are summarized. This paper also contributes to this research topic adding updated results for Altera 65 nm Cyclone III and Xilinx 45 nm Spartan-6 devices.

Implementation of Adaptive Logic Networks on an FPGA board

This work is part of a project that studies the implementation of neural network algorithms in reconfigurable hardware as a way to obtain a high performance neural processor. The results for Adaptive Logic Network (ALN) type binary networks with and without learning in hardware are presented. The designs were made on a hardware platform consisting of a PC compatible as the host computer and an ALTERA RIPP10 reconfigurable board with nine FLEX8K, FPGAs and 512 KB RAM. The different designs were run on the same hardware platform, taking advantage of its configurability. A software tool was developed to automatically convert the ALN network description resulting from the training process with the ATREE 2.7 for Windows software package into a hardware description file. This approach enables the easy generation of the hardware necessary to evaluate the very large combinatorial functions that results in an ALN. In an on-board learning version, an ALN basic node was designed optimizing it in the amount of cells per node used. Several nodes connected in a binary tree structure for each output bit, together with a control block, form the ALN network. The total amount of logic available on-board in the used platform limits the maximum size of the networks from a small to medium range. The performance was studied in pattern recognition applications. The results are compared with the software simulation of ALN networks.

Power estimations vs. power measurements in Spartan-6 devices

Experimental measurements of power consumption for core logic of a 45-nm Spartan-6 FPGA and the comparison with the values predicted by the power estimation tool are presented. The measurement setup, benchmark suite, and EDA flows utilized to obtain power estimations are described. Several types of multipliers implemented in both LUTs and embedded blocks have been utilized as case-studies. They include versions with different levels of pipelining. In addition, a set of actual circuits obtained from OpenCores is analyzed. Main results of power estimations errors are presented and compared.

A soft-core based lab for an introductory microprocessors course

This paper presents a change in the methodology of the laboratory activities in an undergraduate microprocessor systems design course focused on I/O methods and small microprocessors system integration. The laboratory was changed on two main aspects: firstly the assignments are done at home, shortening the time between design activity and experimental verification; secondly a soft-core processor synthesized on an FPGA is exploited to enable the students to exercise hardware design activities on a running system. A suite of development tools combining vendor, third party and in house developed software and hardware cores is presented. These changes are still a work in progress. A transitional version of the course was held during 2011 and the second edition incorporating the rest of the changes is planned for the first half of 2012. Some preliminary results are reported.

Reconfigurable architecture for binary images invariant moment extraction

Moments of the intensity function of a group of pixels have been used fo rthe representation and recognition of objects in two dimensional images. Due to the high computational cost of evaluating the moments, the search for faster computing architectures is very important. This work presents a soft core architecture for the extraction of invariant moments from binary images, using high density logic programmable devices.