Judy B. Shaw

Interfacial oxygen and nitrogen induced dipole formation and vacancy passivation for increased effective work functions in TiN/HfO2 gate stacks

Effective work function (EWF) changes of TiN/HfO2 annealed at low temperatures in different ambient environments are correlated with the atomic concentration of oxygen in the TiN near the metal/dielectric interface. EWF increases of 550 meV are achieved with anneals that incorporate oxygen throughout the TiN with [O]=2.8×1021 cm−3 near the TiN/HfO2 interface. However, further increasing the oxygen concentration via more aggressive anneals results in a relative decrease of the EWF and increase in electrical thickness. First-principles calculations indicate the exchange of O and N atoms near the TiN/HfO2 interface cause the formation of dipoles that increase the EWF.

Characterization of copper voids in dual damascene processes

The introduction of copper dual Damascene processing into integrated circuits has brought about a host of new defectivity issues, especially those related to pitting and voiding. These defects must be understood and eliminated to achieve competitive manufacturing yields and assure device reliability.

Ab initio calculations for industrial materials engineering: successes and challenges

Computational materials science based on ab initio calculations has become an important partner to experiment. This is demonstrated here for the effect of impurities and alloying elements on the strength of a Zr twist grain boundary, the dissociative adsorption and diffusion of iodine on a zirconium surface, the diffusion of oxygen atoms in a Ni twist grain boundary and in bulk Ni, and the dependence of the work function of a TiN-HfO(2) junction on the replacement of N by O atoms. In all of these cases, computations provide atomic-scale understanding as well as quantitative materials property data of value to industrial research and development. There are two key challenges in applying ab initio calculations, namely a higher accuracy in the electronic energy and the efficient exploration of large parts of the configurational space. While progress in these areas is fueled by advances in computer hardware, innovative theoretical concepts combined with systematic large-scale computations will be needed to realize the full potential of ab initio calculations for industrial applications.

Gate-last TiN/HfO2 band edge effective work functions using low-temperature anneals and selective cladding to control interface composition

Silicon N-metal-oxide-semiconductor (NMOS) and P-metal-oxide-semiconductor (PMOS) band edge effective work functions and the correspondingly low threshold voltages (Vt) are demonstrated using standard fab materials and processes in a gate-last scheme employing low-temperature anneals and selective cladding layers. Al diffusion from the cladding to the TiN/HfO2 interface during forming gas anneal together with low O concentration in the TiN enables low NMOS Vt. The use of non-migrating W cladding along with experimentally detected N-induced dipoles, produced by increased oxygen in the TiN, facilitates low PMOS Vt.

Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = −0.20 V consistent with a PMOS EWF =5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF.

Rapid interconnect development using an area accelerated electron beam inspection methodology

This paper describes how a new defect inspection technology and methodology was employed to accelerate the process development and integration learning cycles of a 130 nm advanced logic device. The advanced yield management technique to be described is designed specifically for back-end-of-line (BEOL) module development. Through case studies, the application of this technology for process and integration development is demonstrated. Specifically, we discuss how the application of this technology accelerates the development cycle by allowing for a greater number of cycles of learning. The devices used in this study employed a low k dielectric (k < 3.0), a SiC etch-stop scheme, and several levels of Cu interconnect.

PtSi dominated Schottky barrier heights of Ni(Pt)Si contacts due to Pt segregation

Temperature dependent current-voltage measurements show that the addition of only 10% Pt to NiSi causes an increase of Schottky barrier height (SBH) from 0.65 eV for NiSi to 0.78 eV for the 10% Pt alloy. Internal photoemission measurements resolve two SBHs in all alloyed samples with ≥5% Pt incorporation corresponding to NiSi and PtSi (∼0.68 eV and ∼0.80 eV), proving that each contributes independently to junction current. High angle annular dark field imaging with scanning transmission electron microscopy confirms Pt segregation to the Ni(Pt)Si/Si interface. The resulting increased SBH may therefore be detrimental to contact resistivity in future technology nodes.

Advancement of CMOS Doping Technology in an External Development Framework

The consumer appetite for a rich multimedia experience drives technology development for mobile hand‐held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi‐dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires stro...

Characterization of copper voids in damascene processes

The introduction of copper Damascene processing into integrated circuits has brought about a host of new defectivity issues, especially those related to pitting and voiding. These defects must be understood and eliminated to achieve competitive manufacturing yields and assure device reliability. This paper reviews various defect inspection methodologies that are useful for characterizing copper voids and their electrical effects.

Reduced NiPtSi Schottky barriers by controlling interface composition and new materials incorporation

Contact resistance (Rc) contributes over 65% of the total source to drain series resistance in <; 32 nm CMOS technologies. In this work, reduction of Rc is achieved by lowering the SBH through the incorporation of new materials into NiPtSi. The impact of implanted elemental species as well as alloyed low work function metals is discussed. As diffusion and subsequent interface composition is highly dependent on the incorporated material, these NiPtSi junctions with complex composition are often inhomogeneous, making SBH extraction a less trivial task. Advanced analysis for extracting the true SBH of these junctions will also be presented.