Deborah J. Riley

Comprehensive Evaluation and Study of Pattern Dependency Behavior in Selective Epitaxial Growth of B-Doped SiGe Layers

The influence of chip layout and architecture on the pattern dependency of selective epitaxy of B-doped SiGe layers has been studied. The variations of Ge-, B-content, and growth rate have been investigated locally within a wafer and globally from wafer to wafer. The results are described by the gas depletion theory. Methods to control the variation of layer profile are suggested.

Extraction of correct Schottky barrier height of sulfur implanted NiSi/n-Si junctions: Junction doping rather than barrier height lowering

Proper analysis of the Schottky barrier height extraction methods shows that sulfur implantation followed by anneal does not effectively reduce the Schottky barrier height of NiSi/n-Si contacts. Instead, the results for sulfur implanted samples are consistent with enhanced field emission due to an increased doping density of the surface region of the silicon. Sulfur has a large impact on contact resistivity for silicon with low initial doping concentration ( ∼1017 cm−3). Internal photoemission measurements show that the Schottky barrier height remains unchanged with sulfur implantation.

Layout Variation Effects in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect

This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction.

Material Loss Impact on Device Performance for 32nm CMOS and Beyond

As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.

PtSi dominated Schottky barrier heights of Ni(Pt)Si contacts due to Pt segregation

Temperature dependent current-voltage measurements show that the addition of only 10% Pt to NiSi causes an increase of Schottky barrier height (SBH) from 0.65 eV for NiSi to 0.78 eV for the 10% Pt alloy. Internal photoemission measurements resolve two SBHs in all alloyed samples with ≥5% Pt incorporation corresponding to NiSi and PtSi (∼0.68 eV and ∼0.80 eV), proving that each contributes independently to junction current. High angle annular dark field imaging with scanning transmission electron microscopy confirms Pt segregation to the Ni(Pt)Si/Si interface. The resulting increased SBH may therefore be detrimental to contact resistivity in future technology nodes.

Selective Epitaxial Phosphorus-Doped SiGe Layers for Short-Channel Effect Reduction

Epitaxially grown silicon germanium layers are utilized in very high performance short channel MOSFETs. To reduce short-channel effects, the substrate doping concentration must be increased at the edges of the source and drain. These regions commonly called halos are typically created by ion implantation but the precise positioning of the dopant is a challenge. As devices with embedded SiGe source/drain regions continue to scale, the proximity of the source and drain regions to each other increases the challenge of proper halo placement. This work proposes incorporation of halo placement into the epitaxial deposition process so that dopants are automatically placed where they are needed.

Reduced NiPtSi Schottky barriers by controlling interface composition and new materials incorporation

Contact resistance (Rc) contributes over 65% of the total source to drain series resistance in <; 32 nm CMOS technologies. In this work, reduction of Rc is achieved by lowering the SBH through the incorporation of new materials into NiPtSi. The impact of implanted elemental species as well as alloyed low work function metals is discussed. As diffusion and subsequent interface composition is highly dependent on the incorporated material, these NiPtSi junctions with complex composition are often inhomogeneous, making SBH extraction a less trivial task. Advanced analysis for extracting the true SBH of these junctions will also be presented.