Hiroaki Niimi

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

Specific contact resistivity of n-type Si and Ge M-S and M-I-S contacts

We have theoretically investigated the specific contact resistivity of n-type Si and Ge metal-insulator-semiconductor contacts with various insulating oxides. We have found a significant reduction of the contact resistivity for both Si and Ge with an insertion of insulators at low and moderate donor doping levels. However, at the higher doping levels (>1020 cmu-3), the reduction of the contact resistivity is negligible and the contact resistivity increases as the insulator thickness increase. Thus, we have shown that the lowest possible contact resistivity can be achieved with the metal-semiconductor contact with highest possible activated doping density.

Sub-

We report record low 8.4 × 10^-10 Ω-cm² n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.

10^{-9}~\Omega

We achieved mid-10⁻¹⁰ Ω-cm² n-type S/D contact resistivity (npc) and 1.9×10⁻⁹ Ω-cm² p-type S/D contact resistivity (ppc) by employing laser-induced liquid or solid phase epitaxy (LPE/SPE) of Si:P and Ge:Group-III-Metal metastable alloys inside nano-scale contact trenches. The Ge: Group-III-Metal alloy allows for a metal-Ge Fermi level pinning effect to lower Schottky barrier height (SBH) while reducing both bulk and unipolar heterojunction resistances. Correspondingly, large Ron reduction and Id gain have been realized in scaled n- and p-FinFETs with the contact length of less than 20nm.

-cm2 n-Type Contact Resistivity for FinFET Technology

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys

Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing on transistor parameters, such as Vt and gate stack, defines an upper process boundary and translates to with-in-die (WID Vt variation. Combining DB laser annealing technique with process-friendly layouts enables contact resistance benefit without degrading product level variability.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Contact engineering of Ge-rich source/drain is of critical importance for the development of advanced nano-scale CMOS technology nodes. Germanosilicide or Germanide contacts with low Schottky barrier height are highly desirable to achieve low contact resistance for a Ge-rich source/drain. However, practical integration of Ge-rich SiGe into devices is complicated by its unique physical and chemical properties as compared to Si-rich epitaxial SiGe. We have observed significant erosion along the SiGe interface with its dielectric cap layer. The N2-H2 remote plasma resist strip process has been shown to trigger this erosion when GeO2 exists together with SiO2 at the interface. The integrity of Ge-rich SiGe contact interface can be preserved by replacing the N2-H2 remote plasma resist strip with an O2-based photoresist ash process. Cross-sectional STEM and EDX elemental analysis have confirmed Germanide and Germanosilicide formation at the Ge-rich SiGe contact interface.