Leonardo Gomez

Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gate- controlled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si0.5Ge0.5 hetero- junctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (Vdd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.

Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter

The effects of high-level uniaxial tensile strain on the performance of gate-all-around (GAA) Si n-MOSFETs are investigated for nanowire (NW) diameters down to 8 nm. Suspended strained-Si NWs with ~2-GPa uniaxial tension were realized by nanopatterning-induced unilateral relaxation of ultrathin-body 30% strained-Si-directly-on-insulator substrates. Based on these NWs, GAA strained-Si n-MOSFETs were fabricated with a Si thickness of ~8 nm and NW widths in the range of 50 nm down to 8 nm. The GAA strained-Si MOSFETs show excellent subthreshold swing and cutoff behavior, and approximately two times current drive and intrinsic transconductance enhancement compared to similar unstrained Si devices.

Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs With Body Thickness Ranging From 2 to 25 nm

The electron effective mobility in ultrathin-body n-channel metal-oxide-semiconductor field-effect transistors fabricated on Ge-free 30% strained-Si directly on insulator (SSDOI) is mapped as the body thickness is scaled. Effective mobility and device body thickness were extracted using current-voltage and gate-to-channel capacitance-voltage measurements as well as cross-sectional transmission electron microscopy. Devices with body thicknesses ranging from 2 to 25 nm are studied. Significant mobility enhancements ( ~1.8x) compared to unstrained SOI are observed for 30% SSDOI with body thicknesses of above 3.5 nm. The mobility exhibits a sharp drop as the body thickness is scaled below 3.5 nm

Electron transport in Gate-All-Around uniaxial tensile strained-Si nanowire n-MOSFETs

The intrinsic performance and electron effective mobility of uniaxially strained-Si gate-all-around (GAA) NanoWire (NW) n-MOSFETs are investigated, for the first time. Suspended strained-Si NWs show very high stress (up to ~2.1 GPA) as confirmed by Raman, with no bending of the wires. GAA strained-Si NW n-MOSFETs exhibit excellent subthreshold swing, and current drive and transconductance enhancement of ~2X over unstrained Si control NW devices. The mobility enhancement of these devices over unstrained planar and GAA MOSFETs as well as their scalability to circular NWs with radius of ~4 nm are also demonstrated.

Enhanced Hole Mobility in High Ge Content Asymmetrically Strained-SiGe p-MOSFETs

The hole mobility characteristics of 〈110〉 /(100)-oriented asymmetrically strained-SiGe p-MOSFETs are studied. Uniaxial mechanical strain is applied to biaxial compressive strained devices and the relative change in effective hole mobility is measured. The channel Ge content varies from 0 to 100%. Up to -2.6% biaxial compressive strain is present in the channel and an additive uniaxial strain component of -0.06% is applied via mechanical bending. The hole mobility in biaxial compressive strained-SiGe is enhanced relative to relaxed Si. It is observed that this mobility enhancement increases further with the application of 〈110〉 longitudinal uniaxial compressive strain. The relative change in mobility with applied stress is larger for biaxial compressive strained-SiGe than for Si and increases with the amount of biaxial compressive strain present in the channel.

Asymmetric strain in nanoscale patterned strained -Si/strained -Ge/strained-Si heterostructures on insulator

The engineering of asymmetric strain is demonstrated in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructure on insulator with body thickness of 15nm. Starting material has layers with symmetric in-plane strain, including biaxial strained Si (∼1.8%, tension) and biaxial strained Ge (∼1.8%, compression). Micro-Raman spectroscopy is utilized to characterize the stress in heterostructures patterned into 10-μm-long bars with widths ranging from 300to30nm. Raman measurements are consistent with the transformation from biaxial to uniaxial compressive strain in the Ge for 30-nm-wide bars, as predicated by simulations. Measurements also demonstrate enhanced asymmetric relaxation in the tensile strained Si cap as its thickness is increased.

Fabrication and Characterization of Suspended Uniaxial Tensile Strained-Si Nanowires for Gate-All-Around Nanowire n-MOSFETs

Suspended strained-Si nano-wires (NWs) were fabricated from a highly biaxially strained-Si substrate (with an initial stress of 2.16 GPa). Using e-beam lithography, ~25nm thick NWs with the widths in the range of 20 to 80 nm were fabricated and the stress was investigated by UV micro-Raman spectroscopy. Suspended NWs are strained to an average uniaxial tensile stress level of ~2.1 GPa which is almost independent of NW width, in the range studied in this work. Ultra-dense (25 NWs per micron) sub-20 nm suspended strained-Si NWs were fabricated using resolutionenhanced lithography to improve the Raman signal-to-noise ratio. A tensile in-plane stress level of 1.7GPa was measured for 18 nmwide NWs at 40 nm pitch. Gate-all-around n-MOSFETs were fabricated based on these strained-Si NWs. Electrical measurements on these MOSFETs demonstrate near ideal subthreshold behavior, very high on-to-off ratio and current drive and transconductance enhancement of ~2X over unstrained NWs.

Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire metal-oxide-semiconductor-field-effect-transistors

Si-core/Ge-shell nanowire p-channel metal-oxide-semiconductor-field-effect-transistors with high-permittivity-dielectric/metal-gate have been demonstrated by selective epitaxial growth of Ge thin-films on the Si-nanowires fabricated by a top-down scheme. Cross-sectional transmission-electron-microscopy reveals that the epitaxial Ge shell exhibits hexagonal {111} facets, and that the Ge is defected, particularly near the Si corners. The hole mobility increases by 40% as the Si-core size is decreased from 70 to 20 nm. Finite-element simulations of the stress profile induced in the Ge channel by the gate stack suggest that a transformation in the transverse stress component from compression to tension plays a role in the mobility enhancement.

Performance Enhancement in Uniaxially Tensile Strained-Si Gate-All-Around Nanowire n-MOSFETs

We report, for the first time, the fabrication and characterization of the uniaxially tensile strained- Si gate-all-around (GAA) nanowire (NW) n-MOSFETs. Multi-gate and NW MOSFETs have previously been shown to have excellent electrostatics and immunity to short channel effects. Uniaxially strained-Si in the (110) direction has also been predicted to have the maximum NMOS performance (in terms of electron velocity in Si). One possible technique to create uniaxial tensile Si is to preferentially etch biaxially strained-Si into bars to relax the strain in the transverse direction. Tri-gate MOSFETs based on this technique have been reported. For tri-gate structures, since the mobility of the two (110) sidewalls is less than that of the (100) surface, some of the strain-assisted performance enhancement is reduced. On the other hand, GAA structures utilize the bottom (100) surface to increase the drive current and to reduce the influence of the (110) planes.

Hole velocity enhancement in sub-100 nm gate length strained-SiGe channel p-MOSFETs on insulator

Hole effective mobility and velocity have been extracted from measurements of sub-100 nm gate length strained Si0.45Ge0.55 channel MOSFETs. The hole effective mobility is observed to provide a 2.4x enhancement over Si hole universal mobility for channel lengths in the range of 200 to 80 nm. The extracted virtual source velocity is enhanced by 45% relative to Si control devices. These results are promising for future high-Ge content SiGe-channel p-MOSFETs.