Juergen Wolf

TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules

Silicon interposers with through silicon vias (TSVs) have become important key components of 3D architectures. They are used as intermediate carrier and wiring device for IC components like logics, memories and sensors. Due to custom specific front and back side wiring interposers enable to adapt the fine pitch IO terminals of the mounted ICs to the IO geometries of the package level. High density copper filled TSVs with high aspect ratio as well as high density multi layer wiring using electro plated copper as conductive material and low loss dielectrics enable high performance signal transmission at interposer level without serious losses by parasitic effects. This paper presents the fabrication steps for wafer level processing of silicon interposers with copper filled TSVs as well as their wafer level assembly with IC components. Special focus is drawn on the TSV formation process including via etching, isolation and filling as well as front side high density wiring and subsequent backside processing of the thin TSV wafers. In this context, also temporary wafer to wafer bonding which is required for backside processing of thin TSV wafers is discussed. The final interposers which carry one or more IC components have lateral dimensions up to several square centimeters and thicknesses between 50–100 μm. They include up to several thousands of TSVs per device with a single electrical resistance between 4.9–5.7 mOhms. All processes were run using production equipment at 200 mm wafers.

Fabrication of application specific integrated passive devices using wafer level packaging technologies

Integrated passives have become increasingly popular in the last years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). These IPDs combine different passive components (R, L, C) in one subcomponent to be assembled in one step by standard technologies like SMD or flip chip. In this paper the wafer level thin film fabrication of such IPDs (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization as well as results from the electrical characterization will be discussed.

CrCu based UBM (under bump metallization) study with electroplated Pb/63Sn solder bumps - interfacial reaction and bump shear strength

The electroplating solder bumping process offers fine pitch, high reliability, and cost effective advantages for flip-chip technology. In this technology, under bump metallization (UBM) is required for chemical solder deposition and mechanically reliable solder contact to Al pads. An evaporated Cr/phased CrCu/Cu structure UBM has been used with 95Pb/5Sn and also with 37Pb/63Sn solder for flip-chip interconnection. In this study, the intermediate CrCu layer is modified using various sputtering techniques, and the underlying Cr adhesion layer is compared with TiW. Six UBM systems were selected, and their interfacial reaction and bump shear strength were investigated using 100 /spl mu/m and 50 /spl mu/m size electroplated Pb/63Sn solder bumps. The results demonstrate that the final Cu layer should have a minimum thickness, more than 0.8 /spl mu/m, for interface stability on CrCu based UBMs. Intermetallic compound growth and CrCu layer interface changes are more severe after 20 min reflow at 210/spl deg/C compared with 1000 h aging at 125/spl deg/C. Especially for small size bumps, a more stable interface between UBM and solder bump is required.

Pb-free Sn/3.5Ag electroplating bumping process and under bump metallization (UBM)

Pb-free solder is one of the biggest issues in todays electronic packaging industry. This paper introduces a newly developed Sn/3.5Ag alloy plating process for wafer level bumping. The effects of Under Bump Metallization (UBM) on the process, interfacial reaction, and mechanical strength have been investigated. Four different types of sputtering-based UBM layers-TiW/Cu/electroplated Cu, Cr/CrCu/Cu, NiV/Cu, and TiW/NiV-were fabricated with eutectic Pb/63Sn and Sn/3.5Ag solder. The result shows that the Sn/Ag solder gains Cu or Ni from UBMs and becomes Sn/Ag/Cu or Sn/Ag/Ni during reflow process. Sn/Ag solder has higher reactivity with Cu and Ni than Pb/63Sn. The Intermetallic Compound (IMC) spalling from the interface between UBM/solder has been observed on Cr/CrCu/Cu and TiW/NiV UBMs. However, the IMC spalling phenomena did not decrease the bump shear strength with a bump size of 110 /spl mu/m, whereas a size of 60 /spl mu/m brought a decrease in shear value and failure mode change.

Copper / Benzocyclobutene Multi Layer Wiring - A flexible base Technology for Wafer Level Integration of passive Components

This paper describes the wafer level integration of coils, capacitors and resistors using copper/benzocyclobutene (Cu / BCB) thin film multi layer wiring. Examples for the application of this technology like integration of passives as above chip structures, realization of integrated passive devices as well as fabrication of thin film substrates with integrated passives prove Cu/BCB multi layer wiring to be a versatile base technology for the application-specific integration of passive components. The basic approach of using BCB as dielectric material is discussed to allow integrating high quality, but only small value capacitors in the range of some Pico Farads, which is due to the low dielectric constant of the material. In order to increase the capacitance density a new process allowing to replace the BCB locally by a thin glass layer in the areas of capacitors was evaluated. Since the BCB is only replaced in the areas of capacitors and still present in the other areas of the multi layer construction, the advantages of using BCB as dielectric material for multi layer wiring still apply. The evaluation of the new capacitor dielectric shows, that a 0.5 mum thick glass dielectric features a 26 times higher capacitance density compared to BCB with a thickness of 8 mum, as it has been used in the standard build-up for RF LC-filter integration so far. In order to show the capability of the new glass dielectric regarding size reduction, an existing layout of an integrated passive device with LC-filters is compared with a redesign based on the new technology. By using a 1 mum thick glass layer as dielectric instead of 8 mu thick BCB the total size of the device could be reduced by 28 %.

Development and evaluation of lead free reflow soldering techniques for the flip chip bonding of large GaAs pixel detectors on Si readout chip

Lead free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip chip bonding process for a x-ray pixel detector. Both can be used in pick & place processes with a subsequent batch reflow suitable for high volume production. AuSn solder was selected due to its fluxless bondability, the good wettability and the self-alignment process capability and SnAg solder due to its more ductile behaviour and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured and bumped. Test chips with 55 and 170 mum pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating Au first and Sn on top. Au bumps were also formed on substrate side. Two under bump metallizations (UBM) were used for the SnAg samples: Cu and Ni. FE simulation was performed for AuSn and SnAg interconnections and for different chip sizes. A local model was designed for the bump interconnection and a global octant model for the whole assembly. Very high values were calculated for the peel stress using AuSn bumps. SnAg bumps on the other hand showed a 3 to 5 times reduced peel stress dependent on the chip size. A flip chip bonding process setup was carried out for both solder types, AuSn as well as SnAg, with an analysis of the samples by electrical measurements, cross sectioning and SEM. Due to the different coefficients of the thermal expansion (CTE) of GaAs and Si no stable bonding process was found for the AuSn modules as predicted by the FE analysis. With increasing chip size failures like pad lift or cracking of the GaAs were observed. The SnAg samples showed good bonding results. This technology was then selected to assemble test modules for thermal cycling between -55 and +125degC comparing the Cu and Ni UBM. The modules were qualified by electrical monitoring as well as cross sectioning. More than 200 cycles were reached by the 55 mum pitch, 16.3 mm square, bonded GaAs chips and about 400 by the smallest, 4 mm square chips, although no underfilling was used. As failure mode a fracture within the solder was detected. Based on experimental and simulation results functional 256 times256 GaAs pixel detectors with a chip size of 14 times14 mm2 were assembled on Si read out chips using SnAg bumps on a Cu UBM. Finally, these x-ray image sensors were wire bonded to a PCB and successfully tested showing a yield (on pixel-level) of about 98%.

Stackable thin film multi layer substrates with integrated passive components

Visionary concepts for future electronic systems, which are ubiquitous, extremely miniaturized and serve a wide range of services, are extremely challenging for current system integration and packaging technologies. In the meaning of hetero system integration different integration techniques, such as 3D integration, integration of passive components and assembly of thin chips, have to be combined to enable a further increase in package density. This paper describes an approach for 3D system integration using thin stackable substrates with high density interconnection layers, which include integrated inductors, capacitors and resistors. After a brief overview of the different passive test structures, which were exclusively designed for the evaluation of this approach, the process flow for the technological realization of the substrates were presented. Some results of the electrical characterization of the fabricated integrated passive structures were discussed. Finally initial results for the stacking of the substrates were presented

MEMS IC test probe utilizing fritting contacts

The emerging MEMS technologies are entering in an active phase of high volume production and successful commercial applications. The expertise and the qualification for space application of such devices have already begun. But these technologies are still recent and important efforts on the reliability issue have to be done. This paper defines the role of technological analysis in the actual MEMS design process. Afterwards, it presents MEMS technological analysis techniques developed at CNES applied to an open MEMS technology. In particular, it is shown how these technological analyses response to designer needs and that the designer and the founder still need a strong interaction. We also present the MEMS reliability issue at CNES and replace it in the current worlds one.

Silicon-interposer with high density Cu-filled TSVs

A silicon-interposer technology with high density Cu-filled TSVs and Cu-based redistribution layers was realized. Test structures in a process control module were used for electrical characterization.

Cu passivation with self-assembled monolayers for direct metal bonding in 3D integration

Direct metal bonding is a preferred fine-pitch technology for stacking of Si dies in 3D integration. Cu is a metal of choice for direct metal bonding because it is the most common metal for redistribution layer in advanced semiconductor manufacturing, Cu has high conductivity and it is a low cost candidate. However Cu oxidises very fast in air which makes the bonding procedure challenging. In this study we present the novel technique of Cu passivation with temporary protective self-assembled monolayer (SAM). X-ray photoelectron spectroscopy (XPS) analysis was used in order to carry out the chemical analysis of the Cu surface. Contact angle (CA) measurements provided the information about the monolayer formation. The influence of immersion time and storage conditions on the SAM passivation quality was examined. Storage of a coated Cu surface at low-temperature air conditions was found to be a promising technique for a long-term oxidation retarding. We summarize the key substrate parameters that influence SAM protective capability.