Juhoon Yoon

Development of chip-on-chip with face to face technology as a low cost alternative for 3D packaging

This paper describes the ongoing research and development at Amkor Technology of Chip-on-chip/Face to Face (CoC/F2F) technology being developed in parallel with Through Silicon Via (TSV) package assembly. Unlike other 3D packaging techniques using TSVs that require front end processing, CoC/F2F technology uses existing chip attach (C/A) or thermal compression (TC) equipment to connect each die - referred to as the mother die and daughter die for the larger and smaller ICs, respectively. The cost to assemble CoC/F2F is relatively inexpensive, making it an attractive alternative to TSV for many applications. Some of these include the integration of ASIC with logic, MEMS with ASIC, microcontroller with memory, and optoelectronic module with microcontroller.

Development of Next Generation Flip Chip Interconnection Technology Using Homogenized Laser-Assisted Bonding

Conventional flip chip technologies such as the mass reflow (MR) process and the thermal compression bonding (TCB) process are commonly used technologies in the micro assembly field. However, there is a continuous need for next generation interconnection technology to achieve a low form factor with increasing die and substrate complexities. Moreover, very thin 3D integrated packages and 2.5D packages with thin interposer die promise advanced interconnection technologies for mobile and wearable applications. With this point of view, the most important factor in interconnection is optimal thermal energy control for soldering. However, a conventional MR process cannot provide any selectivity and controlled thermal energy transferring with the traditional convection reflow. Its high thermal budget makes warpage an issue, aside from other side effects. To overcome the MR process problems, recent researches and industries have focused on developing a TCB process with non-conductive paste (NCP) or non-conductive film (NCF) due to TCBs unique advantages of low mechanical and thermal stress. However, the productivity of the TCB process is not comparably to the conventional process. Laser-assisted bonding (LAB) with beam homogenizer is considered to be the next generation interconnection technology due to its excellent thermal selectivity, extremely fast ramping up speed with purely controlled wavelength. This LAB process offers a very stable interconnection quality as well as robust functional and reliability result. Interestingly, it also achieves excellent results with thin coreless substrate due to its selective heating area availability. This paper will discuss the laser heating mechanism, multi-chip & component bonding availability and advantage of LAB from an assembly industrial perspective.

Copper foil exposed structure for thin PoP warpage improvement

Advanced flip chip packaging technology supports the next generation of products with increased die complexities. The increase in complexity and functionality has been driving the need to investigate fine-pitch interconnection technology with 3D integration. Recently, Package on Package (PoP) has emerged as the preferred 3D integration of logic processors and memory devices for mobile handsets and portable applications. The current PoP solution consists of memory die in the top package stacked on logic function die in the bottom package. Various challenges also need to be met to support the volume production and establish reliable manufacturing process for PoP platform. Among the available key technologies, the TMV (Through Mold Via) solution has been widely adopted to reduce package warpage, achieve a fine-pitch PoP and stabilize stacking performance. Furthermore, since the trend towards thinner phones continues, it is essential to reduce the thickness of PoP to meet market requirement. However, controlling warpage is one of main concerns to generate a thin PoP TMV structure. In this paper, a copper foil exposed package, which has a thin copper foil with adhesive layer film, is introduced as a new PoP bottom package structure. It was laminated on the die backside to improve warpage behavior at room and evaluated temperatures. Based on simulation and experimental results, it was concluded warpage amount and direction depend on thickness and thermo mechanical properties of the copper foil as well as the adhesive material. The best combination was selected for best warpage behavior not only for the bottom package but also PoP stacked warpage to see if it could improve high package stacking yield performance.

Strip grinding introduction for thin PoP

Due to rapid growth in the mobile industry, Package-on-Package (PoP) has been widely adopted for 3D integration of logic and memory devices within mobile handsets, and other portable multimedia products, etc. Typical PoP configuration includes a logic function in the bottom package while memory dice are assembled into the top package. The TMV solution is widely adopted to reduce package warpage, to achieve a fine pitch PoP, and to stabilize stacking performance. Another big benefit of the TMV is to generate a thin structure by exposing the back side of the die using a film assist mold system. However, the trend of mobile devices is going thinner and thinner, and there is a limitation to achieve the thin PoP structure. The most difficult barrier to generate the thin PoP structure is the warpage control. In this paper, a strip grinding process is introduced as a solution to generate thinner PoP structures in overmolded packages. Applying the strip grinding process to exposed die, reducing mold clearance, and exploring double sided mold structures to reduce die/package height were also investigated.

Fine pitch PoP introduction

Package-on-package (PoP) has been widely adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. Typical PoP solution is applied to logic processor as bottom package and memory device as top package. TMV® solution is being applied to reduce the warpage and achieve the fine pitch PoP and stable stacking performance. Currently, 0.4mm MIF(Memory Interface Pitch) is the minimum pitch under production and more fine MIF pitch is being requested because more functions are being integrated on chip then chip size becomes larger even wafer node is going narrower. To sustain the similar package size with larger chip size, fine pitch PoP is required. In this paper, 0.3 and 0.27mm MIF pitch PoP will be studied as a solution for fine pitch PoP and as a interface material between Top and Bottom package, solder ball and Cu post will be evaluated.