Choonheung Lee

Application of through mold via (TMV) as PoP base package

In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.

Study of interconnection process for fine pitch flip chip

Today, flip chip technology is a main stream of interconnection in microelectronic packaging and market forces continue to drive toward finer pitch interconnections. In this paper, fine pitch flip chip (FPFC) interconnection technology (i.e., less than 60um pitch) will be described. Two types of 50um pitch bump (Au stud & Cu pillar) will be evaluated and two different flip-chip (FC) bonding methods will be studied. Package structures of bare die flip-chip CSP (chip scale package) and also over molded version will be studied for reliability performance and volume assembly fit. For characterization, structure analysis will be performed at each reliability read point. Finally this paper will conclude by identifying the most robust bonding method for the FPFC devices.

Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array

System-in-package provides highly integrated packaging with high-speed performance. Many SiP packages contain low-cost 3D stacked chips interconnected by fine wire bonds. In a high-frequency spectrum, these wire bonds can cause discontinuities causing signal degradation. This article addresses problems with wire bonding in high-frequency SiP packages and proposes design methodologies to reduce these discontinuities

Development of large die fine pitch flip chip BGA using TCNCP technology

Recently, technologies related to Fine Pitch Flip Chip or FPFC have been great achievements for various next generation devices, allowing a significant increase in the number of signal I/O and achieving low form factor packages. Consequently, fine pitch Cu pillar flip chip Chip Scale Package (CSP) with small sized die, with package dimension of less than 16×16mm, is already under high volume production using the Thermal-Compression Bonding with Non-conductive Paste (TCNCP) technology [1-2]. In the case of Flip Chip Ball Grid Array (FCBGA), there is a growing need for FPFC technology with Cu pillar in supporting next generation silicon node. However, there will be a high possibility of yield drop issue in conventional mass-reflow process and potential reliability due to the highly concerned tensile stress between low k die and substrate by CTE mismatch especially at the edge of the die. This can be a critical quality issue for fine pitch devices compared to normal pitch (i.e., 150um) flip chip BGA. Therefore, TCNCP bonding as an alternative should be studied on fine pitch Cu pillar flip chip BGA. This paper will discuss fine pitch flip chip assembly technology for large sized flip chip BGA. Two kinds of assembly method, mass reflow bonding versus thermal compression bonding, for the flip chip bonding will be compared for the large FPFCBGA package. Meanwhile, the advantage of TC bonding with pre-applied underfill process will be described. For robust interconnection between die and substrate for large FPFCBGA, the result of the bonding test will be described with several surface finishes such as ENEPIG, Direct Immersion Gold (DIG), Immersion Tin (IT), and Solder Coating on substrate. Interestingly, one of selected surface finishes has shown excellent reliability test results. Finally, this paper will discuss an effective approach for fine pitch devices from an assembly perspective.

Molded underfill development for flipstack CSP

The current standard for flipchip encapsulantion is a two step process. Following flipchip attach, a liquid underfill material is dispensed along the die edge and allowed to flow, via adhesive capillary force, through the gap between the flipchip die and the PCB. Upon cure of the liquid underfill, complete die encapsulation is achieved with a standard transfer mold process using preformed epoxy pellets. When applied to a FlipStack™ CSP product, a matrix of die on the substrate are individually underfilled and cured. The transfer molding process then encapsulates all die in a single transfer of the molding compound.

Characterization of intermetallic compound (IMC) growth in Cu wire ball bonding on Al pad metallization

As one of the alternative materials in chip interconnection, copper wire has become popular because of its lower cost and higher electrical conductivity than gold wire. Moreover it is known that long term reliability performance at high temperature of copper wire is better than that of gold wire because of slower Cu/Al intermetallic compound (IMC) growth than that of Au/Al intermetallics. However, majority of copper wire bonding development works has been focused on the material and/or process optimization and qualification so far, now it is time that we need to understand more on the Cu/Al IMC growth behavior to prevent IMC related failures in copper wire field application. So, in this paper, we aimed to generate Cu/Al IMC growth model based on the experimental result depends on high temperature storage (HTS) time and temperature and also tried to suggest Cu/Al IMC thickness guideline to minimize IMC degradation. In this experiment, Al pad chips were bonded with 99.99% purity of copper wire and Pd coated copper wire and some of them were encapsulated with epoxy mold compound. The samples were storaged at the temperature range from 150 C to 250 C upto 1000 hrs. IMC phase and thickness were analyzed by the help of SEM and EDX. In order to generate Cu/Al growth model, reaction rate (K) and activation energy (AQ) were calculated with above experimental results by using Arrhenius diffusion equation. Also, in order to investigate the Cu/Al IMC effect on the bondability, ball shear strength was measured and its result was correlated with IMC thickness. According to this paper, we could derive Cu/Al IMC thickness prediction model and suggest IMC thickness guideline that can minimize IMC failures.

Board level reliability assessments of thru-mold via package on package (TMV™ PoP)

In recent years, Package-on-package (PoP) has been adopted as major application package platform in 3D integration of logic and memory devices. However, as electronic technology developed, higher technology requirements are requested in packaging. Amkor Technology, Inc introduced the next generation PoP solution to meet the next generation technology requirements in 2008 by the using of TMV™ technology which incorporates a laser ablation process that is conducive to current matrix-molded semiconductor assembly techniques. The next generation PoP platform named as TMV™ PoP has been qualified in all package level qualification tests. Also in board level reliability tests, BLR TC & drop performances are similar or better than those of the conventional PoP.

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.

Board level reliability study on three-dimensional thin stacked package

This paper discusses the optimal design for PS-etCSP to achieve reliable thermal fatigue life of solder joint. For this purpose design analysis was performed using both simulation and experimental approaches. Since reduction of warpage is most critical issue to ensure good solder joint connection for thin packages, parametric study was performed to find the optimal set of package outline dimensions using finite element method. Next to find the optimal design far solder joint reliability, 3D FEA fatigue model was established with non linear material properties of solder joint. Various factors such as ball land size, motherboard thickness and surface mounting type were studied. As a result, it is found that thin die with small size and small CTE molding compound is better for minimizing package warpage and larger opening size, thinner board and single mounting on board are good for solder joint reliability. The stack of package however has little effect on solder joint reliability. The effects of board thickness and surface mounting type (single/double) were investigated in terms of assembly stiffness and solder joint reliability. Simulation results showed good correspondence with experiment. The fatigue life and failure location predicted by simulation agreed well with experimental data. The fatigue life of optimal design was 1225 cycles for single PS-etCSP and 990 cycles for stacked PS-etCSP with single side mounting on board under the thermal cycling loading of temperature of -40/spl deg/C/spl sim/125/spl deg/C. Subsequently it can be concluded that optimal design of PS-etCSP can meet the requirement for most portable product applications.

Evaluation and verification of enhanced electrical performance of advanced coreless flip-chip BGA package with warpage measurement data

In this paper, the 8+1-layer coreless substrate of fcBGA will be introduced, which was revised from the 12-layer core substrate. This coreless substrate was manufactured in Shinko using an advanced ABF film (GZ41) having low CTE for lower warpage and better assembly performance. To evaluate and verify the electrical performance, the fabricated coreless substrate was measured for S- and Z-parameters in frequency-domain and measured for differential TDR impedance and eye-diagram & timing jitter histogram in time-domain. The simulated and measured results were compared with the simulated results of the 12-layer core substrate for evaluation of the improvement from signal/power integrity. In order to evaluate the assembly performance of the coreless substrate, the warpage data and basic material data (Tg, CTE) were measured and demonstrated for die attach area and non-die area.