DaeByoung Kang

Application of through mold via (TMV) as PoP base package

In recent years, package-on-package (PoP) has been rapidly adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. However, existing methods of making the PoP base package may not satisfy next generation applications that will require reduced memory interface pitches, higher memory interface pin-counts, reduced thickness, tight warpage control and higher levels of integration within the PoP base package. This paper introduces a new PoP base package structure that addresses the challenges of next generation applications. A PoP base package with through mold vias (TMV) will be described. Package flatness and package stacking results will be presented and advantages of TMV technology will be reviewed.

Next generation fine pitch Cu Pillar technology — Enabling next generation silicon nodes

There has been a growing need for fine pitch flip chip technology in support of next generation communication devices with increasing die complexities. The increase in functionality which drives a larger number of signal I/Os in combination with small die size requirements as a result of transistor size reductions have driven the need to investigate finer die interconnect pitches. Traditional solder or Cu Pillar interconnect pitches of 150um to 200um that are currently used in both low and high end flip chip applications are now facing a number of technical limitations as device scaling requirements push the limits of flip chip pad density per square mm of silicon. This paper will review the process development and advancement of several next generation fine pitch Cu Pillar bumping and assembly processes, with pitches less than 60um, that are focused on addressing the challenges seen on silicon nodes such as 65nm and beyond.

Study of interconnection process for fine pitch flip chip

Today, flip chip technology is a main stream of interconnection in microelectronic packaging and market forces continue to drive toward finer pitch interconnections. In this paper, fine pitch flip chip (FPFC) interconnection technology (i.e., less than 60um pitch) will be described. Two types of 50um pitch bump (Au stud & Cu pillar) will be evaluated and two different flip-chip (FC) bonding methods will be studied. Package structures of bare die flip-chip CSP (chip scale package) and also over molded version will be studied for reliability performance and volume assembly fit. For characterization, structure analysis will be performed at each reliability read point. Finally this paper will conclude by identifying the most robust bonding method for the FPFC devices.

Multi-die chip on wafer thermo-compression bonding using non-conductive film

Advanced chip on wafer (CoW) assembly has emerged as a key assembly technology for enabling advanced silicon nodes and complex integration. Traditional assembly methods for chip attach have proven capable in this approach, but suffer in the area of fillet design rules. Non-conductive films have been in development as a replacement to the liquid pre-applied underfill materials used in fine pitch copper pillar assembly; however implementation has been slowed by unfavorable cost of ownership and low throughput. Results from recent development have proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chip on wafer format. The results of this scale up will help move the industry toward a process that can deliver advanced assembly design rules at a cost competitive position when compared to incumbent technologies.

Development of chip-on-chip with face to face technology as a low cost alternative for 3D packaging

This paper describes the ongoing research and development at Amkor Technology of Chip-on-chip/Face to Face (CoC/F2F) technology being developed in parallel with Through Silicon Via (TSV) package assembly. Unlike other 3D packaging techniques using TSVs that require front end processing, CoC/F2F technology uses existing chip attach (C/A) or thermal compression (TC) equipment to connect each die - referred to as the mother die and daughter die for the larger and smaller ICs, respectively. The cost to assemble CoC/F2F is relatively inexpensive, making it an attractive alternative to TSV for many applications. Some of these include the integration of ASIC with logic, MEMS with ASIC, microcontroller with memory, and optoelectronic module with microcontroller.