Julian A. B. Dines

Smart pixel optoelectronic receiver based on a charge sensitive amplifier design

The application of charge sensitive amplifier techniques to the design of receivers within smart pixel optoelectronic systems is presented. An example optical input amplifier is given which should provide high sensitivity (/spl plusmn/0.3 /spl mu/A differential), low power consumption (0.6 mW) and small area usage (50 /spl mu/m/spl times/20 /spl mu/m) for operation at a conventional CMOS bit rate of 100 Mb/s. The minimum (simulated) optical switching energy is 6 fJ.

Design and construction of an optoelectronic crossbar switch containing a terabit per second free-space optical interconnect

The completed detailed design and initial phases of construction of an optoelectronic crossbar demonstrator are presented. The experimental system uses hybrid very large scale integrated optoelectronics technology whereby InGaAs-based detectors and modulators are flip-chip bonded onto silicon integrated circuits. The system aims to demonstrate a 1-Tb/s aggregate data input/output to a single chip by means of free-space optics.

Perfect-shuffle interconnected bitonic sorter: optoelectronic design

The algorithmic, electronic, and optical aspects of the implementation of a perfect-shuffle interconnected bitonic sorter are analyzed. The performance metrics such as the bit output data rate and the power consumption of the system are quantified. The sorting module is designed to demonstrate the parallel nonlocal interconnection of smart-pixel arrays and the use of optical-image control masks in a functioning information processor.

Optical Interconnectivity in a Scalable Data-Parallel System

Scalability. Few would disagree that the future of high-performance computing lies with massively parallel systems(MPS), since there are major physical limitations to the clockrate of a single processor. Massively parallel systems arerequired to be scalable in the sense that their performanceshould be proportional to the number of processors. However,a feasible architecture for a scalable massively parallel systemis still wanting, as true, i.e., unlimited scalability is not onlytheoretically impossible but even in the practical sense cannotbe achieved on a range of more than an order of magnitude inthe number of processors. Whatever a system’s architecture,interconnect, or programming model, something will not scale:the throughput or latency of the interconnect, its cost, orthe synchronization overheads. Since all these componentscontribute to performance in different ways, the issue of scal-ability is a very complex one indeed.So in what sense can one argue for scalability of massivelyparallel systems? There have been quite a few attempts todefine it (see [1]) on the basis of some strong assumptionsregarding the nature of parallel computation. The mostcommon assumption that is being made in such analyses is thatthe processors run some predominantly local processes whichrequire little external communication (it manifests itself in theparameter “communication to computation ratio” assumed tobe small and used in all but a few performance models). Bymigrating these self-contained processes and placing severalof them per processor to balance out computational workacross the system, it is believed that scalability may beachieved without requiring physically unfeasible networkingand/or dramatically different computational models. In reality,however, process concurrency of such kind continues to facevarious fundamental limitations from data mapping to dynamicload balancing to program paradigm issues.Data parallelism. We would like to address a simpler, andin our view more promising, way of doing parallel computing

Optoelectronic systems based on InGaAs–complementary-metal-oxide-semiconductor smart-pixel arrays and free-space optical interconnects

Free-space optical interconnects have been identified as a potentially important technology for future massively parallel-computing systems. The development of optoelectronic smart pixels based on InGaAs/AlGaAs multiple-quantum-well modulators and detectors flip-chip solder-bump bonded onto complementary-metal-oxide-semiconductor (CMOS) circuits and the design and construction of an experimental processor in which the devices are linked by free-space optical interconnects are described. For demonstrating the capabilities of the technology, a parallel data-sorting system has been identified as an effective demonstrator. By use of Batchers bitonic sorting algorithm and exploitation of a perfect-shuffle optical interconnection, the system has the potential to perform a full sort on 1024, 16-bit words in less than 16 mus. We describe the design, testing, and characterization of the smart-pixel devices and free-space optical components. InGaAs-CMOS smart-pixel, chip-to-chip communication has been demonstrated at 50 Mbits/s. It is shown that the initial system specifications can be met by the component technologies.

Development of free-space digital optics in computing

To someone with an electronics or computer science background, many of optical computings concepts may seem outlandish. Optics grew out of applied physics and still retains many aspects of that heritage. This is in contrast to digital computings roots in electronics. Recent efforts have been made to bring optical computing more in line with microelectronic engineering. Perhaps that will speed the acceptance of opto-electronic technology. The authors describe their research into optical devices for data communication. They are investigating free-space optics, the propagation of optical signals through the air using lenses and mirrors to focus and redirect the beams. The advantages of free-space optics, derive from their large spatial bandwidth and physical channel density. Like the human eye, which takes in an enormous amount of information in parallel, a low-cost lens can provide more than a million independent connections. The authors aim to exploit optoelectronic computings capability for such massively parallel data transfers.

Performance analysis of self-electro-optic-effect-device-based (SEED-based) smart-pixel arrays used in data sorting

The performance factors associated with self-electro-optic-effect-device-(SEED-) based smart-pixel arrays are analyzed in terms of semiconductor technology and pixel complexity. The sorting task is chosen as a practical example. Complementary metal-oxide semiconductor (CMOS)-SEED 2 × 2 self-routing nodes operated with quasi-cw-mode lasers are shown to provide the maximum processing power and on- or off-chip communication rate. The need for new front-end amplifiers for the smart-pixel technology is emphasized.

Operation of an optoelectronic crossbar switch containing a terabit-per-second free-space optical interconnect

The experimental operation of a terabit-per-second scale optoelectronic connection to a silicon very-large-scale-integrated circuit is described. A demonstrator system, in the form of an optoelectronic crossbar switch, has been constructed as a technology test bed. The assembly and testing of the components making up the system, including a flip-chipped InGaAs-GaAs optical interface chip, are reported. Using optical inputs to the electronic switching chip, single-channel routing of data through the system at the design rate of 250 Mb/s (without internal fan-out) was achieved. With 4000 optical inputs, this corresponds to a potential aggregate data input of a terabit per second into the single 14.6 /spl times/ 15.6 mm CMOS chip. In addition 50-Mb/s data rates were switched utilizing the full internal optical fan-out included in the system to complete the required connectivity. This simultaneous input of data across the chip corresponds to an aggregate data input of 0.2 Tb/s. The experimental system also utilized optical distribution of clock signals across the CMOS chip.

Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology

The Scottish Collaborative Initiative in Optoelectronic Sciences (SCIOS) is developing an optoelectronic parallel sorter using CMOS/InGaAs hybrid technology. We describe the design of a system with the potential of sorting 1024 8-bit words in 10 /spl mu/s. The system is based on 32-by-32 arrays of smart pixels produced by solder-assembly of strained InGaAs/GaAs MQW modulator/detectors with CMOS electronics. These devices are linked by an optical perfect shuffle interconnect. The functionality of each processing node, as required by the algorithm, is selected by optical control signals which are circulated along with the optical data. Various physical constraints, including optics limitations, laser power requirements and heat dissipation, have been investigated.

Multimode planar lightwave circuits using direct write of polymers

The performance of a novel acylate-based thermally stable photo-polymer is presented. Rapid direct writing of the guides and other structures is realized using a high-power 325 nm He:Cd laser. The loss is measured by cut-back to be less than 0.17 dB/cm at 850 nm and less than 0.5 dB/cm at 1310 nm. This material and writing system is used to make 50 micrometers square core cladded guides and compliant bumps for device attachment, and 45 degree(s) TIR mirrors for out of plane coupling.