Julian Wolf

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability

The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing predictability of every feature provided by the processor.

RTOS Support for Parallel Execution of Hard Real-Time Applications on the MERASA Multi-core Processor

Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. However, currently available multi-cores are not feasible to be used in safety-critical environments with hard real-time constraints. Hard real-time tasks running on different cores must be executed in isolation or their interferences must be time-bounded. Thus, new requirements also arise for a real-time operating system (RTOS), in particular if the parallel execution of hard real-time applications should be supported. In this paper we focus on the MERASA system software as an RTOS developed on top of the MERASA multi-core processor. The MERASA system software fulfils the requirements for time-bounded execution of parallel hard real-time tasks. In particular we focus on thread control with synchronisation mechanisms, memory management and resource management requirements. Our evaluations show that all system software functions are time-bounded by a worst-case execution time (WCET) analysis.

WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core

To meet performance requirements as well as constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question of timing analysability is raised with these architectures. In the MERASA project, a WCET-aware multicore processor has been designed with the appropriate system software. They both guarantee that the WCET of tasks running on dierent cores can be safely analyzed since their possible interactions can be bounded. Nevertheless, computing the WCET of a parallel application is still not straightforward and a high-level preliminary analysis of the communication and synchronization patterns must be performed. In this paper, we report on our experience in evaluating the WCET of a parallel 3D multigrid solver code and we propose lines for further research on this topic.

A Fault Detection and Recovery Architecture for a Teradevice Dataflow System

Future computing systems (Teradevices) will probably contain more than 1000 cores on a single die. To exploit this parallelism, threaded dataflow execution models are promising, since they provide side-effect free execution and reduced synchronization overhead. But the terascale transistor integration of such chips make them orders of magnitude more vulnerable to voltage fluctuation, radiation, and process variations. This means reliability techniques have to be an essential part of such future systems, too.In this paper, we conceptualize a fault tolerant architecture for a scalable threadeddataflow system. We provide methods to detect permanent, intermittent, and transientfaults during the execution. Furthermore, we propose a recovery technique for dataflow threads.

Large drilling machine control code — Parallelisation and WCET speedup

Hard real-time applications in safety-critical domains — namely avionics, automotive, and machinery — require high-performance and timing analysability. We present research results of the parallelisation and WCET analysis of an industrial hard real-time application, i.e. the control code of a large drilling machine from BAUER Maschinen GmbH. We reached a quad-core speedup of 2.62 for the maximum observed execution time (MOET) and 1.93 on the WCET compared to the sequential version. For the WCET analysis we used the measurement-based WCET analysis tool RapiTime.

A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks

Multicore processors can deliver higher performance than single-core processors by exploiting thread level parallelism (TLP): applications are split into independent threads, each of which is mapped into a different core, reducing the execution time and potentially its worst-case execution time (WCET). Unfortunately, inter-thread interferences generated by simultaneous accesses to shared resources from different threads may completely destroy the performance benefits brought by TLP. This paper proposes a software/hardware cache partitioning approach that reduces the inter-thread memory interferences generated in hard real-time software-pipelined parallel applications. Our results show that our approach effectively reduces memory interferences, while still guaranteeing a predictable timing behaviour, achieving a WCET estimation reduction of 28% for a software pipelined version of the LU decomposition application with respect to the single-threaded version.

Fine-grained timing and control flow error checking for hard real-time task execution

Robustness and reliability are essential requirements of todays embedded systems. Especially errors in the control flow of a program, e.g. caused by transient errors, may lead to a faulty system behavior potentially with catastrophic consequences. Several methods for control flow checking have been proposed during the last decades. However, these techniques mostly focus on a correct sequence of application parts but not on the correct timing behavior of the control flow, which is essential for hard real-time systems. In this paper, we present a new approach which introduces fine-grained on-line timing checks for hard real-time systems combined with a lightweight control flow monitoring technique. The proposed approach is a hybrid hardware-software technique: We instrument the application code at compile-time by adding checkpoints, which contain temporal and logical information of the control flow. During run-time, a small hardware check unit connected to the core reads the instrumented data in order to verify the correctness of the applications control flow and timing behavior. The finegrained functionality of our mechanism allows a detection of many transient errors, associated with very low detection latency. It is no longer necessary to redundantly execute code in order to monitor anomalies. The hardware overhead is limited to a small check unit (only 0.5 % of chip space compared to the processor core); according to experimental results, the execution time overhead is only 10.6 % in the average case while the memory overhead is 12.3 %.

Fault coverage of a timing and control flow checker for hard real-time systems

Dependability is a crucial requirement of todays embedded systems. To achieve a higher level of fault tolerance, it is necessary to develop and integrate mechanisms for a reliable fault detection. In the context of hard real-time computing, such a mechanism should also guarantee correct timing behavior, an essential requirement for these systems. In this paper, we present results of the fault coverage of a lightweight timing and control flow checker for hard real-time systems. An experimental evaluation shows that more than 30% of injected faults can be detected by our technique, while the number of errors leading to an endless loop is reduced by around 80 %. The check mechanism causes only very low overhead concerning additional memory usage (15.0% on average) and execution time (12.2% on average).

UbiMASS Ubiquitous Mobile Agent System for Wireless Sensor Networks

Ubiquitous systems build on the vision that great amounts of fixed and mobile microchips and sensors will be integrated in everyday objects. Developing services on basis of sensor nodes and limited devices is an arduous task. A program running on such a device is static and limited to a single service. If a new service needs to be performed, devices have to be fundamentally reprogrammed and reloaded. For dynamic service distribution a mobile agent system is devised and services are distributed by mobile agents. The idea in this paper is to load a service on a limited device or sensor node when it is needed and to switch services dynamically. The service comes in form of an agent to each device. We developed a mobile agent system called UbiMASS that is downsized to run on sensor nodes. UbiMASS was evaluated on the sensor nodes ESB430 which has multiple sensors and actuators on-board. For real test scenarios, we could investigate the possibility and advantages of service changes on a wireless sensor network using mobile agents. UbiMASS offers an easy and convenient way to dynamically reprogram tiny devices with wireless connections.