Juliano Benfica

On the comparison of synchronous versus asynchronous circuits under the scope of conducted power-supply noise

Nowadays, the major part of electronic devices make use of synchronous circuits controlled by a global clock signal. However, the noise sensitivity as well as the electromagnetic emission of this type of circuit is very high. In this context, asynchronous circuits represent a very interesting solution, since they are naturally more robust than the synchronous counterparts. The proposed work aims at comparing the robustness of synchronous and asynchronous circuits generated according to the Desynchronization Approach presented in when they are exposed to power supply disturbances (PSD). To provide the necessary results to compare the two different design paradigms, we performed a set of experiments according to the IEC 61.000-4-17 and the IEC 61.000-4-29 Normatives. The obtained results demonstrate that the asynchronous circuit is significantly more robust than the synchronous one.

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects

This work proposes a novel methodology to evaluate SRAM-based FPGAs susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, TotalIonizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGAs VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGAs BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined Effects of Conducted EMI and TID

This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.

Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs

This paper presents a new approach based on a watchdog infrastructure intellectual property (I-IP) core to detect control-flow faults that affect CPU execution time. More precisely, this approach aims at detecting those faults that change the expected CPU instruction sequence and that as consequence, change also (by increasing or reducing) the expected CPU time allocated for the execution of the monitored task. The underlined advantage of this approach is the ability of detecting faults in systems-on-chips (SoCs) simultaneously running multiple tasks under the control of a real-time (preemptive) operating system (OS). In this multi-task scenario, the I-IP performs fault detection in a time-shared basis. Practical experiments based on the IEC 62.132-2 Std. for IC electromagnetic immunity measurement have been carried out and the obtained results are discussed.

Evaluating the Effects of Combined Total Ionizing Dose Radiation and Electromagnetic Interference

Although measurement methods for Electromagnetic (EM) immunity and Total Ionizing Dose (TID) radiation are highly standardized, little effort has been made though, to evaluate the behavior of embedded systems under the combined effects. Considering realistic environment conditions only the measurement of these effects can guarantee reliable embedded systems for critical applications. A configurable platform to evaluate the effects of TID radiation and EM Interference (EMI) on embedded systems is presented. Experiments illustrate the consequences regarding delay and fault occurrence probability as well as current consumption and minimum power supply.

Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity

The roadmap for standardization of electromagnetic (EM) immunity measurement methods has reached a high degree of success with the IEC 62.132 proposal. The same understanding can be taken from the MIL-STD-883H for total ionizing dose (TID) radiation. However, no effort has been performed to measure the behavior of electronics operating under the combined effects of both, EM noise and TID radiation. For secure embedded systems and systems-on-chip (SoC) devoted to critical applications, these combined-effect measurements are mandatory. In this paper, we present a configurable platform devoted for combined tests of EM immunity and TID radiation measurements of prototype embedded systems. The platform attends the IEC 62.132–2 (for radiated EM noise), IEC 61.0004–17 and IEC 61.0004–29 (for conducted EM disturbance) and 1019.8 method for TID Test Procedure of MIL-STD-883H.

Configurable platform for SoC combined tests of TID radiation, aging and EMI

The roadmap for standardization of electromagnetic (EM) immunity measurement methods has reached a high degree of success with the IEC 62.132 proposal. The same understanding can be taken from the MIL-STD-883H for total ionizing dose (TID) radiation and burn-in (for aging purpose). However, no effort has been performed to measure the behavior of electronics operating under the combined effects of EM noise, TID radiation and aging. For secure embedded systems and systems-on-chip (SoC) devoted to critical applications, these combined-effect measurements are mandatory. In this paper, we present a configurable platform devoted to perform these combined tests on FPGA-prototyped SoC. The platform attends the IEC 62.132-2 (for radiated EM noise), IEC 61.000-4-17 and IEC 61.000-4-29 (for conducted EM disturbance) and methods 1019.4 for TID and 1015.9 for Burn-in Test Procedures of MIL-STD-883H.

Evaluating the use of a platform for combined tests of total ionizing dose radiation and Electromagnetic immunity

Although measurement methods for Electromagnetic (EM) immunity and Total Ionizing Dose (TID) radiation are highly standardized, no effort has been made to evaluate the behavior of embedded systems under the combined effects. Considering realistic environment conditions only the measurement of these effects can guarantee reliable embedded systems for critical applications. A configurable platform to evaluate the effects of TID radiation and EM Interference (EMI) on embedded systems is presented. Experiments illustrate the consequences regarding delay and fault occurrence probability as well as current consumption and minimum power supply.

Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID

This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.