Julien Denoulet

High performance motion detection: some trends toward new embedded architectures for vision systems

The goal of this article is to compare some optimised implementations on current high performance platforms in order to highlight architectural trends in the field of embedded architectures and to get an estimation of what should be the components of a next generation vision system. We present some implementations of robust motion detection algorithms on three architectures: a general purpose RISC processor—the PowerPC G4—a parallel artificial retina dedicated to low level image processing—Pvlsar34—and the Associative Mesh, a specialized architecture based on associative net. To handle the different aspects and constraints of embedded systems, execution time and power consumption of these architectures are compared.

Empirical Method Based on Neural Networks for Analog Power Modeling

We introduce an empirical method for power consumption modeling of analog components at system level. The principal step of this method uses neural networks to approximate the mathematical curve of the power consumption as a function of the inputs and parameters of the analog component. For a node of a wireless sensors network, we found an average error of 1.53% with a maximum error of 3.06% between our estimation and the measured power consumption. This novel method is suitable for Platform-Based Design and has three key features for architecture exploration purposes. Firstly, the method is generic as it can be applied to any analog component in any modeling and simulation environment. Secondly, the method is suitable for the total (analog and digital) power consumption estimation of a heterogeneous system. Thirdly, the method provides an online estimation of the instantaneous power consumption of analog blocks.

Implementing motion Markov detection on general purpose processor and associative mesh

We present a robust implementation of a motion detection algorithm based on a Markovian relaxation both on general purpose processors, and on a specialized architecture, the associative mesh. The mesh architecture is an instance of the associative nets model targeting real time execution of low level image algorithms and vision-SoC implementation. The algorithm implementation on both architectures is described, and also the required optimizations to speedup the execution.

Modelling field bus communications in mixed-signal embedded systems

We present a modelling platform using the SystemC-AMS language to simulate field bus communications for embedded systems. Our platform includes the model of an I/O controller IP (in this specific case an C controller) that interfaces a master microprocessor with its peripherals on the field bus. Our platform shows the execution of the embedded software and its analog response on the lines of the bus. Moreover, it also takes into account the influence of the circuitss I/O by including their IBIS models in the SystemC-AMS description, as well as the bus lines imperfections. Finally, we present simulation results to validate our platform and measure the overhead introduced by SystemC-AMS over a pure digital SystemC simulation.

Modeling I 2 C Communication Between SoCs with SystemC-AMS

In this paper, we show how to mode the I2C bus communications between the nodes of an embedded system. For this purpose, we use the SystemC-AMS model of an I2C bus controller IP based on the PFC8584. Then we show how this IP can be included into two kinds of embedded systems nodes: on the one hand a 8051 micro-controller node, on the other hand a MIPS based SOC node. Finally the simulation results show the successful operation of the multi-master I2C bus communications between these two nodes in SystemC-AMS. Moreover the SystemC-AMS simulation introduces a small 10% overhead over the digital SystemC simulation for the two nodes multi-master I2C communication.

Signal Integrity-Aware Virtual Prototyping of Field Bus-Based Embedded Systems

In this paper, we introduce a modeling methodology for field bus-based embedded systems that allows dynamic evaluation of their signal integrity characteristics at the virtual prototyping step. Our methodology is based on the following criteria: 1) a signal integrity-aware I/O interface mixed model; 2) a physical model of transmission lines to estimate signal degradation caused by the bus lines; and 3) an ICEM model to estimate the impact of a chips internal activity on its power voltage or its I/O. Through simulations and experimental validations, we show that our methodology allows functional validation of the design and can also evaluate some low-level effects such as the influence of an embedded software instruction on the voltage drops in the power rails.

An OFDMA based RF interconnect for massive multi-core processors

A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.

High level modeling of signal integrity in field bus communication with SystemC-AMS

This paper presents a novel method for modeling the functionality of a mixed-signal system, and analyzing its signal integrity (SI) at a high-level of abstraction with SystemC-AMS. Our model includes on a unique platform a functional module and a non-functional module. The functional module represents the operative behavior of the system and the non-functional module, based on neural network techniques, displays the SI characteristics of the system. The proposed method is demonstrated by modeling field bus communication system with two nodes. We achieved an error of about 3% for the neural network based Time Data Flow (TDF) model with respect to a RLC Electrical Linear Networks (ELN) model.

An architecture based on reconfigurability and asynchronism for real-time image processing

This paper presents the evolution of the Associative Mesh, a massively parallel SIMD architecture based on reconfigurability and asynchronism. To favor its System on Chip implementation, we introduce a reorganization of the structure based on processors virtualization and evaluate its consequences on hardware cost and algorithmic performances. Using an evaluation environment based on a programming library and a parameterized description of the architecture, we show that a virtualized Associative Mesh achieves real-time execution for a number of complex image processing algorithms, including split and merge segmentation, watershed segmentation and motion detection.

A Dynamically Reconfigurable RF NoC for Many-Core

With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic reconfiguration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF~NoC becomes faster with 32 nodes, achieving a x3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to x6 lower latency while ensuring fairness.