Jun-Chau Chien

A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-mum CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 231-1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10-12 are 300 and 10 mVpp, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68times0.8 mm2 where the active circuit area only occupies 0.32times0.6 mm2

Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection

In this paper, the locking range of the injection-locked ring oscillators is investigated. To improve the injection efficiency and the locking range for superharmonic frequency division, a multiple-injection technique is proposed. Using a 0.18-mum CMOS process, a wideband frequency divider based on a three-stage ring oscillator is implemented for demonstration. With a tunable free-running frequency, the fabricated circuit provides 2:1 and 4:1 frequency division with a single-ended input signal ranging from 13 to 25 and 30 to 45 GHz, respectively. Compared with the case of the single-ended injection, the locking range of the frequency divider almost doubles when multiple-input injection with optimum phases is utilized. The experimental results exhibit good agreement with the theoretical derivation and the circuit simulation.

Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture

The design of a wide-tuning-range millimeter-wave CMOS VCO is presented in this paper. In contrast to the conventional wideband topologies, a nonuniform standing-wave oscillator utilizing tapered gain elements, switched transmission lines and distributed varactors is employed to provide an extended output range with the coarse and fine frequency tuning. Due to the use of the transmission line architecture and the position-dependent amplitude of the standing waves, the loading effects of the varactors and the MOS switches can be alleviated, enabling the VCO to operate at higher frequencies. Using a 0.18-mum CMOS process, a 40-GHz VCO is designed and implemented. Consuming a DC power of 27 mW from a 1.5-V supply voltage, the fabricated circuit exhibits a frequency tuning range of 7.5 GHz with an output power level ranging from -13.6 to -4 dBm. The measured phase noise at 1-MHz offset is lower than -96 dBc/Hz within the entire frequency range. This work demonstrates the widest tuning range in percentage among the CMOS VCOs at millimeter-wave frequencies.

40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.

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An injection-locked ring oscillator fabricated in a 0.18-/spl mu/m CMOS process is presented for high-speed applications. By tuning the free-running frequency, the proposed circuit provides 2:1 and 4:1 frequency division over a wide input frequency range. The measured input frequency range covers 16.7-25.2 GHz and 41.2-46.9 GHz for 2:1 and 4:1 frequency division, respectively. The divider core operates at a 1.8-V supply voltage with a power consumption between 21.0 and 23.8mW for the entire frequency tuning range.

CMOS

A millimeter-wave multiphase voltage-controlled oscillator (VCO) is presented. In order to facilitate high-frequency oscillation and to minimize the phase error caused by the device and layout mismatch, a rotary traveling-wave topology based on transmission lines with inductive loading is employed for the circuit implementation. Using a 0.18-mum CMOS process, the fabricated VCO provides half- quadrature output phases at 32 GHz. The measured output power and phase noise at 1-MHz offset are -9 dBm and -108 dBc/Hz, respectively. Operated at a supply voltage of 1.2 V, the power consumption of the proposed circuit is 54 mW.

A wide-band CMOS injection-locked ring oscillator

A tunable transimpedance amplifier (TIA) is presented in this letter. By incorporating a mechanism for gain and bandwidth tuning, the TIA can be adjusted to achieve optimum circuit performance with a lowest bit-error-rate (BER) for high-speed applications. The proposed circuit is implemented in a 0.18-mum CMOS process. Consuming a dc power of 34mW from a 2.0-V supply voltage, the fabricated TIA exhibits a variable -3-dB bandwidth from 3.9 to 7.6GHz while maintaining a transimpedance gain of 52dBOmega. With a 7.5-Gb/s 231-1 pseudo-random bit sequence, the measured input sensitivity of the TIA is -19 dBm at a BER of 10-12

A 32-GHz Rotary Traveling-Wave Voltage Controlled Oscillator in 0.18-

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-mum SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6plusmn 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage

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By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-mum CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps

CMOS

This study presents a device for protein detection using a low-pass radio frequency filter with gold nanoparticles (AuNPs). Self-assembled multilayer gold nanoparticles were immobilized on the sensing surface of the filter by sandwich immunoassay. The measured frequency of the filter ranges from 50MHzto30GHz. The multilayer gold nanoparticles result in a change of 3dB bandwidth of the low-pass filter. Results show that 1ng∕μl of RIgG solution can be detected after triple-layer AuNPs are completely formed. The change in 3dB bandwidth increases with the concentration of target protein. Therefore, this device has potential for protein quantification.