Chin-Shen Lin

A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier

A 0.5-14-GHz distributed amplifier (DA) using 0.18-/spl mu/m CMOS technology has been presented. It demonstrates the highest gain bandwidth product reported for a CMOS amplifier using a standard Si-based IC process. This DA chip achieves measured results of 10.6/spl plusmn/0.9 dB gain, NF between 3.4 and 5.4 dB with good return losses better than from 0.5 to 14 GHz. The measured output IP3 and P/sub ldB/ are +20 dBm and +10 dBm, respectively, from 2 to 10 GHz.

Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode

The designs of two fully integrated CMOS cascode distributed amplifiers (DAs) with 14-GHz and 22-GHz bandwidth are presented. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. These amplifiers demonstrated the highest frequency and widest bandwidth of operation for amplifiers using regular CMOS processes to date. This paper also describes the analysis to design the cascode CMOS DA, together with the small-signal models, EM simulation of the spiral inductors on the silicon substrate, and the analysis of the cascode device. Good agreement between measured and simulated results was achieved for both of the DA designs.

Analysis of Multiconductor Coupled-Line Marchand Baluns for Miniature MMIC Design

The analysis and systematic design procedure for multiconductor coupled-line Marchand baluns are presented in this paper. A simple two-conductor coupled-line model is used to analyze the Marchand balun and simplify the analysis significantly. Two monolithic balanced frequency doublers with miniature Marchand baluns are implemented to verify the design procedure. Both the chips achieve the smallest chip sizes at their operating frequencies with comparable performance.

A Fundamental 90-GHz CMOS VCO Using New Ring-Coupled Quad

A new circuit topology, named ring-coupled quad for millimeter-wave voltage controlled oscillator (VCO) design, is proposed. The proposed circuit topology provides higher open loop voltage gain than conventional cross-coupled pair. The layout of the proposed ring-coupled quad is fully symmetric without additional interconnection lines. A 90-GHz VCO using 90-nm CMOS process is implemented with this ring-coupled quad. This 90-GHz oscillator demonstrates a 2.5-GHz tuning range and higher than -20dBm output power. The proposed ring-coupled quad is suitable for the realization of high frequency VCOs

FET-integrated CPW and the application in filter synthesis design method on traveling-wave switch above 100 GHz

A new transmission-line concept, called the field-effect transistor (FET)-integrated coplanar waveguide (CPW), is proposed. This concept treats the passive two-finger FET as CPW and, thus, the scaling rule is more accurate than the previous model, especially in high frequency. The extraction approach of the parameters of the FET-integrated CPW is also included. With this concept, the design procedure of traveling-wave switches can be equivalent to a filter synthesis problem. Based on this design procedure, a single-pole single-throw and a single-pole double-throw traveling-wave switch have been realized and measured using 0.15-/spl mu/m high-linearity AlGaAs/InGaAs/GaAs pseudomorphic high electron-mobility transistors. Finally, the frequency limitation of the traveling-wave switches is also discussed. The results show the FET-integrated CPW is the most efficient way to overcome the frequency limitations of traveling-wave switches, achieving operation frequency to 135 GHz, the highest frequency reported to date.

A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-mum SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6plusmn 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage

Analysis and Design of Reduced-Size Marchand Rat-Race Hybrid for Millimeter-Wave Compact Balanced Mixers in 130-nm CMOS Process

The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design methodology. The monolithic microwave integrated circuit mixers achieve comparable performance with a compact chip size among the reported 60-GHz CMOS mixers.

A Compact 60 GHz Integrated Up-Converter Using Miniature Transformer Couplers With 5 dB Conversion Gain

A 60 GHz singly balanced subharmonic up-converter is presented in this letter. The monolithic microwave integrated circuit (MMIC) chip is implemented using a standard 0.13 mu m mixed-signal/radio frequency (RF) CMOS process. This circuit combines a subharmonic mixer and a three-stage cascode output amplifier. A new miniature transformer coupler is used to provide the local oscillation (LO) signals with 90deg phase difference to achieve subharmonic mixing. This MMIC demonstrates a conversion gain of 5 dB for RF frequency from 58 to 66 GHz, and the 2LO-to-RF isolation is over 40 dB. The chip size is only 0.366 mm 2.

A low-voltage and variable-gain distributed amplifier for 3.1-10.6 GHz UWB systems

A low-voltage and variable-gain distributed amplifier is presented in this letter. This microwave monolithic integrated circuit amplifier achieves 12-dB gain with a 3-dB frequency band of 1.6-12.1GHz and 6.5-dB noise figure under the bias condition of 0.8-V supply voltage and 6.4-mW total dc power consumption. The gain-control range is from -18dB to +20dB. Resistive metal-oxide-semiconductor field-effect transistors are used as termination resistors to compensate the mismatch due to different bias conditions. From 3.1 to 10.6GHz, the maximum gain ripple of this amplifier is only /spl plusmn/1dB for the gain level between -4 and 20dB.

A 14∼23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection

A broadband MMIC frequency distributed doubler fabricated by 0.18-μm CMOS technology has been designed to operate from 14 to 23 GHz. In order to reject the fundamental signals, the traditional low-pass drain line was replaced by a high-pass structure. The topology can improve the fundamental rejection without additional balanced structure, thus the chip size can be minimized. This measured conversion loss is less than 14 dB and the fundamental rejection is better than 22 dB for the output frequency between 14 and 23 GHz. The chip size is only 0.54 × 0.38 mm2.