Jun-Gi Jo

Current Reusing VCO and Divide-by-Two Frequency Divider for Quadrature LO Generation

For low-power and accurate quadrature local oscillator (LO) signal generation, an LC-tank voltage controlled oscillator (VCO) operating at double the required LO-frequency reuses the bias current of divide-by-two frequency divider. The current reusing VCO and divide-by-two frequency divider are targeted to generate the LO signals for a 1.57 GHz global positioning system receiver. Implemented in a 0.18 mum CMOS technology, the current reusing VCO and divide-by-two frequency divider consumes 1.7mA from a 1.8 V supply. The measured phase noise is -120dBc/Hz at 1 MHz offset when the carrier frequency is 1.57GHz.

An

A dual-mode RF receiver with low-IF architecture has been developed for L1-band Global Positioning System (GPS) and Galileo system in a 0.18- mum CMOS process. The channel-selecting bandpass filter centered at 4.092 MHz has programmable bandwidth (2.046 MHz, 4.092 MHz), which allows the reception of GPS and Galileo signals. A fractional-N phase-locked loop generates the local oscillator signals, which allows multiple reference clock frequencies, and in turn, share of a reference oscillator with other systems. The noise figure of the receiver is 4.5 dB, while consuming 41.4 mW from a 1.8-V supply. The image signal is rejected by more than 34 dB.

L1

A 20-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13-μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) digital-to-analog converter (DAC) for feedback. A new data weighted averaging (DWA) technique is developed to remove the timing bottleneck at 640 MHz clock frequency. The CT SDM achieves 63.9 dB peak signal-to-noise-and-distortion ratio (SNDR) and 68 dB dynamic range (DR) which decreases by only 2.3 dB when the RMS jitter of the 640 MHz clock is 15.6 ps. The power consumption is 58 mW from a 1.2-V supply.

-Band Dual-Mode RF Receiver for GPS and Galileo in 0.18-

A 20MHz bandwidth continuous-time ΣΔ modulator with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) DAC for feedback. A new data weighted averaging (DWA) technique is adopted to remove the timing bottleneck at 640MHz clock frequency. The modulator achieves 63.9dB peak-SNDR. Dynamic range is 68dB and decreases by only 2.3dB when RMS clock jitter is 15ps. The power consumption is 58mW from a 1.2V supply.

\mu {\hbox{m}}

A 1.2V 10MHz low-pass Gm-C filter implemented with low-voltage Gm-cell based on passive resistor and triode-region MOSFET is described. The Gm-cell converts the input voltage to the output current by passive resistor for wider signal swing. For low-voltage operation, triode-region MOS transistors are widely used while the output resistance is improved by regulated gate cascode circuit. The 10MHz low-pass Gm-C filter was implemented in a 0.13/spl mu/m CMOS technology and the measured input third order intercept point is 3dBV and 9.5dBV, respectively for in-band and out-of-band input.

CMOS

A dual-mode RF receiver with low-IF architecture has been developed for L1-band GPS and Galileo in a 0.18 mum CMOS process. The channel selecting bandpass filter centered at 4.092 MHz has programmable bandwidth (2MHz, 4 MHZ, and 6 MHz), which allows the reception of GPS and Galileo signals. A fractional-N phase locked loop generates local oscillator, allowing multiple reference clock frequencies. The noise figure of the receiver is 4.5 dB while consuming 41.4 mW from a 1.8 V supply. The image signal is rejected by more than 34 dB.

A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA

A system-on-chip (SoC) has been developed in a 130-nm CMOS technology that converts HDMI input to MHL output and allows a mobile handset to display its video contents on a large screen television (TV) or monitor. The functionalities of the SoC have been verified by the compliance tests specified by the HDMI and MHL standards.

A 20MHz bandwidth continuous-time ΣΔ modulator with jitter immunity improved full-clock period SCR (FSCR) DAC and high speed DWA

A clock and data recovery (CDR) circuit has been developed for a clock-forwarded 3.4-Gbps serial link. The loss of the signal channel is compensated by a linear equaliser whose output is applied to eight samplers which provides edge- and data-samples of the serial data input. Based on the edge- and data-samples, the phase of a voltage-controlled oscillator (VCO) running at one-fourth of the data rate is adjusted to get the optimum eight-phase sampling clocks. Implemented in a 0.13-μm standard CMOS process, the CDR circuit shows the bit-error rate (BER) less than 10−15.