Jun-Kyu Lee

Wafer-Level Flip Chip Packages Using Preapplied Anisotropic Conductive Films (ACFs)

Recently, wafer-level packaging (WLP) has become one of the promising packaging technologies due to its advantages, such as fewer processing steps, lower cost, and enhanced device performance compared to conventional single-chip packaging. Many developments on new WLP design, material, and process have been accomplished according to performance and reliability requirement of the devices to be packaged [1], [2]. For a lower cost, higher performance, and environmentally green packaging process, anisotropic conductive film (ACF) flip chip assembly has been widely used, such as in ultrafine-pitch flat panel display (FPD) and general semiconductor packaging applications, too. However, there has been no previous attempt on the wafer-level flip chip assembly using ACFs. In this paper, wafer-level flip chip packages using preapplied ACFs were investigated. After ACF prelamination on an electroplated Au bumped wafer, and subsequent singulation, singulated chips were flip-chip assembled on an organic substrate using a thermocompression bonding method. Au-plated bumps were well assembled on Ni/Au pads of organic substrates. The electrical, mechanical properties and the reliabilities of wafer-level flip chip assemblies (WL-FC As) were evaluated and compared with conventional ACF flip chip assemblies using the thermocompression method. Contact resistance measurement was performed after thermal cycling, high temperature/humidity, and pressure cooker test. ACF joints between electroplated Au bumps and substrate metal pads showed stable contact resistance of 5 mOmega per a bump, strong bump adhesion, and similar reliability behaviors compared with conventional ACF flip chip joints using a thermocompression bonding. As a summary, new wafer-level packages using preapplied ACFs were successfully demonstrated for flip chip assembly. The new wafer-level packages using preapplied ACFs can be widely used for many nonsolder flip chip assembly applications such as chip-on-board (COB), chip-on-flex (COF), and chip-on-glass (COG).

Cu/SnAg Double Bump Flip Chip Assembly as an Alternative of Solder Flip Chip on Organic Substrates for Fine Pitch Applications

Recently, the need of fine pitch flip chip interconnection has been continuously growing. In spite of this trend, solder flip chip interconnections have reached the limit in fine pitch applications of less than about 150 mum pitch, because bump bridging between adjacent solder bumps occur. Therefore, the investigation on the fine pitch flip chip structure and its reliability are being needed. Metal column and solder double layered (^double bump) flip chip structure is one of the candidates for fine pitch applications. Double bump flip chip structure provides three advantages: (1) fine pitch flip chip interconnection less than 150 mum due to straight shape of metal column bumps, (2) better thermo-mechanical reliability by changing the height of metal column bumps, and (3) high current-carrying capability due to excellent electrical conductivity of Cu as one of the column bump materials. In this study, Cu (60 mum) / SnAg (20 mum) double bump flip chip were investigated as one of the promising fine pitch interconnections. We successfully demonstrated Cu/SnAg double bump flip chip assembly with 100 mum pitch on organic PCB substrates without bridged bumps by optimizing the bonding conditions such as bonding temperature profile, bonding force and flux. Assembled Cu/SnAg double bump joints had stable contact resistance of 12~14 mOmega. And then, we studied interfacial reactions and reliability evaluation of Cu/SnAg double bump flip chip assembly. Cu3Sn, Cu6Sn5, Ni3Sn4, (Cu,Ni)6Sn5, and Ag3Sn IMCs were formed at Cu/SnAg double bump joints after the additional reflow and solid-state aging. Excessive IMC growth and the formation of Kirkendall voids can be one of the origins which can deteriorate mechanical and electrical reliability of flip chip joints. All Cu/SnAg double bumps showed stable contact resistance after 1000 hours 85degC/85%RH test. And, Cu/SnAg double bumps generally maintained their initial contact resistance after high temperature storage test but showed slightly increased resistance at 150degC due to the formation of Kirkendall voids. On the other hand, contact resistance increased after thermal cycling test. After 1002 cycle T/C test, the failure at Si chip and bump interface was observed in corner and edge bumps. However, center bumps still maintained their contact even after 1000 T/C cycles. The main cause of thermal cycling failures was the Al and Ti UBM depletion between Si chip and Cu column bumps

Improvement of wettability and drop impact reliability by Al addition in SnAgCu solder

SnAgCu solder is most popular solder composition system in the package industry. Therefore, SnAgCu solder has been studied by many researchers to improve its properties. In this study, we ran tests to verify the effect of Al additive metal in SnAgCu solder in term of wettability and drop impact reliability. The test solder compositions were Sn1.0Ag0.5Cu solder (Ref. solder) and Sn1.0Ag0.5Cu-xwt%Al solder and Al contents were 0.005, 0.01, 0.02, 0.1, and 0.12wt%.

Improvement of drop shock and TC reliability for large die Wafer Level Packages in mobile application

In this study, board level drop shock and TC reliabilities in terms of solder materials and UBM(Under Bump Metallurgy) structures have been evaluated to suggest optimal structures of WLP(Wafer level Packaging) with the large die, high pin counts for mobile application. Test vehicles of WLP have been designed with 5.6×5.6mm die size, 340 um thickness (including backside protection film), 14×14 ball array, 400 um ball pitch. Firstly, effect of solder ball composition has been investigated through BLR(Board Level Reliability) tests using electroplated Cu UBM with which solder compositions are SAC305, SAC125-0.05Ni, SAC105, Sn0.7Cu respectively. Secondly, effect of UBM structure has been confirmed under SAC305 ball composition, with which UBM structures are Cu UBM, Ni base-UBM, and direct ball attaching without UBM. Additionally, effect of dielectric materials and thickness for the reliability has been investigated. For the condition of BLR tests, drop tests have been performed under JEDEC Condition B (1500G, 0.5millisecond duration, half-sin pulse), as listed JESD22-B110. Resistance variation was observed by in-situ electrical monitoring during drop test. In case of TC test, the condition was −45~125 D, 2cph (cycles per hour), and resistances of daisy chain were measured every 100cycles. Lifetime statistics for WLP with each design and factors have been compared through the Weibull plot for cumulative failure rate after TC and drop shock tests, respectively. Also, the observation of fracture mode through cross-section analysis and FEM simulation for the thermo-mechanical fatigue has been conducted to define the failure mechanism for each reliability test.

Study on the characteristics of various dopants in Sn-1Ag-0.8Cu solder

Recently, the Sn-Ag-Cu system alloy has been widely used in the packaging (PKG) industry a replacement for conventional SnPb solders. The Sn-Ag-Cu system alloy was divided into two types, high Ag solder and low Ag solder composition, according to Ag content. Generally, high Ag solder, as Sn-3∼4Ag-0.5Cu, showed good thermal cycle (TC) reliability because of excellent creep resistance and thermal fatigue reliability, but it showed poor drop impact reliability compared to SnPb solder or low Ag solder. Meanwhile, low Ag solder as Sn-0.3∼1.2Ag-0.5Cu showed better drop shock reliability than high Ag solder, but it showed poorer TC reliability. These results mean that just a change in Ag content in the SAC alloy cannot simultaneously improve TC and drop impact reliability.

Effect of surface pad finish on fracture mode of flip chip package under electro-migration

Electro-migration effect in Cu-OSP and ENIG pad finish in flip chip package were investigate. A temperature of 398 K with a current density of 1.5×104A/cm2 was applied. For EM phenomena were investigated using SAC solder composition of different pad finish. The diameter of the bumps was about 100 mm. Through this research, the main fracture types can be represented by two types : 1) failure caused by voids in the solder; 2) failure caused by Cu wiring. And the movement of Sn, Ag and Cu atoms in solder bump were able to confirm.

Development on integrated passive devices using wafer level package technologies

In recent years, as the demand for ever-smaller electronic systems grows, Industry trends are seeking ways to increase IC integration levels and to reduce the size and weight of IC packages. The explosive expansion of mobile electronic terminals generates strong demand for high-performance, cost-effective and miniaturized RF modules providing desired wireless connectivity. The chip scale package (CSP) and wafer-level packaging (WLP) resulting from this effort, have been introduced into industry at an unprecedented rate. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of systems in package (SiP). So, WL-IPDs technology will provide as integration and embedding technology of passive device in the systems in package(SiP). These IPDs combine different passive components (R, L, C) in one subcomponent to be assembled in one step by standard technologies like SMD or flip chip. In this paper the wafer level fabrication and electrical performance of such IPDs (WL-IPDs) will be discussed. We have developed the LPF (Low Pass Filter) in combination with spiral inductor and MIM (Metal-Insulator-Metal) Capacitor. Spiral inductor was demonstrated 8µm thick Cu film of inductor structure, to reduce the inductor resistance, and 20µm thick dielectric material, separates inductor structure and silicon wafer to reduce the substrate loss. The Quality factor is over 30 at 2 GHz with inductance of 0.6 nH. MIM Capacitor was fabricated using SI3N4 as Insulation material and the Unit capacitance obtained 1.08nF/mm2. Also, Insertion loss of 0.14dB and 0.11dB for 3rd order filter and 5th order filter at 2.4 GHz respectively was achieved through both front-end process capable of high uniformity insulator deposition and back-end process capable of forming thick Cu RDL(Redistribution). A good matching between measured value and simulated one using 3D simulator was achieved

Study of drop-performance improved lead-free solder by PCB pad finish

This study aimed to evaluate the drop reliability using Ag content and metal additives in a Sn-Ag-Cu system composition. In this study, the main compositions of the solder ball were Sn1.0Ag0.5Cu and Sn0.5Ag0.5Cu, respectively, and Ni and Co elements were additions a additive element. The PCB plating was used Cu-OSP, Immersion Sn, Electroplated Ni/Au, and ENEPIG (electroless Ni electroless Pd immersion Sn). The drop properties of Sn0.5Ag0.5Cu and Sn1.0Ag0.5Cu-Ni were improved by about 20% and 15%, respectively compared to that of the Sn1.0Ag0.5Cu solder ball. The Sn1.0Ag0.5Cu-Ni solder ball improved by about 15% compared to the Sn1.0Ag0.5Cu solder ball. These results are because the absorption of drop impact is increased due to the modulus and the yield strength of the solder ball are decreased by lower Ag content and Ni additives. Generally the interface IMCs between the Cu-UBM and Sn-Ag-Cu solder ball is a Cu6Sn5. But the Cu6Sn5 IMC is changed to (Cu,Ni)6Sn5 IMC, and the growth rate of the IMC is decreased by a Ni additive. The interface IMCs between Ni-UBM and the solder ball were (Cu,Ni)6Sn5, regardless of solder composition and additives. In this study, Sn0.5Ag0.5Cu-Ni solder composition was shown the best drop property that was improved about 35% compared with the Sn1.0Ag0.5Cu solder ball in all test conditions.

Studies on double-layered metal bumps for fine pitch flip chip applications

In this paper, Cu/SnAg double-layered bumps structure was proposed and investigated for the fine pitch flip chip applications. Test chip was designed considering the recent high speed memory device and its pad size and pitch was 60/spl mu/m and 100/spl mu/m, respectively. Cu and SnAg bumps were fabricated as a 60/spl mu/m and 20/spl mu/m thickness on SiO/sub 2//Ti/TiN/Al/TiW/Cu on Si wafer using the electroplating method. Test chip was flip chip assembled with PCB substrates using thermo-compression bonding method. Because the pitch was very tight, the flip chip bonding of Cu/SnAg double bumps was very difficult and it affected several bonding parameters such as bonding pressure, temperature, time, Cu bump diameter and so on. The bonding results were evaluated through the cross-sectional image of interconnection and the electrical continuity test of daisy chain and bump resistance using 4-point Kelvin structure. The long time reliability tests like thermal cycling test and 85/spl deg/C/85% test are now in progress after flip chip bonding and underfill dispensing.