Jun Ohtani

A shared built-in self-repair analysis for multiple embedded memories

A shared built-in self-repair analysis scheme (Shared-BISA) for multiple embedded memory cores in the SOC is proposed to realize minimum area penalty independent of the number of embedded memory cores. A compact reconfigurable CAM array in the BISA circuitry realizes a flexible redundancy analysis structure to cope with various memory core and redundancy structures, and a high-speed operation up to 500 MHz.

A 90-MHz 16-Mb system integrated memory with direct interface to CPU

This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM and control circuitry including a TAG. This system memory realizes a computer system without glue chips. Thus, this system memory brings a computer system which is low cost, low power and compact size with sufficient performance. The maximum operating frequency is 90 MHz and the operating current at cache hit is 156 mA.