Katsumi Dosaka

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7- mu m CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm/sup 2/ is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity. >

Test cost reduction by at-speed BISR for embedded DRAMs

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SoC) device test. This paper proposes putting the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM using low cost automatic test equipment (ATE). The area of the BISR is approximately 1.7 mm/sup 2/, about 2% of conventional SoC devices. Using an error storage table form contributes to realizing a small area penalty of the repair analysis function. e-DRAM functional test time was reduced about 20% less than the conventional method at wafer level testing. Moreover, the results of e-DRAM test and repair analysis using BISR is almost coincident with the conventional method.

An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

Embedded DRAM (eDRAM) macros have been proposed as away to achieve the low power and wide bandwidth required by graphic controllers, network systems, and mobile systems. Currently, these applications require a reduction of design turn-around time (TAT) for the various specifications, as well as lower-voltage operation. Conventional eDRAM is generated by placement of hardware macros that are designed beforehand. The hardware macro restricts eDRAM specifications, and many hardware macros are necessary to support the demands of different customers. An eDRAM architecture that provides only the interface component as a software macro, i.e., hardware description language (HDL), has been recently reported. However, in this architecture, adjusting of control signal delays and differing control circuits are necessary for each memory configuration. The architecture reported here provides reduction of design TAT, more than 120 k eDRAM configurations, 1.2 V (100 MHz) to 1.8 V (200 MHz) operation, and a flexible interface. In addition, an enhanced on-chip tester tests the various eDRAM macros, reducing test time to 1/64 with a simultaneous 512 b I/O pass/failjudgment, and performs repair analysis at speed testing conditions.

Design methodology of embedded DRAM with virtual-socket architecture

This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRAM control circuitry with the DRAM memory array is handled as a hardware macro, resulting in the increase in design TAT. On the other hand, our proposed architecture provides the DRAM control circuitry as a software macro to take advantage of the automated tools based on synchronous circuit design. With array-generator technology, this architecture can achieve high quality and quick turn-around time (QTAT) of flexible embedded DRAM that is almost the same as the CMOS ASIC. We applied this virtual-socket architecture to the development of the 61-Mb synchronous DRAM core using 0.18-/spl mu/m design rule and confirmed the high-speed operation, 166 MHz at CAS latency of two, and 180 MHz at that of three. The experimental results show that our proposed architecture can be applied to the development of the high-performance embedded DRAM with design QTAT.