Masaki Kumanoya

Analysis of coupling noise between adjacent bit lines in megabit DRAMs

Different bit-line structures, bit-line materials, widths, spacings, and passivation materials were fabricated to analyze the effect of the coupling noise between adjacent bit lines in megabit DRAMs. Each component of total bit-line capacitance was measured to obtain the bit-line-to-bit-line capacitance and the other contributions to the total bit-line capacitance. Accelerated soft error tests were performed on each sample. The results suggest the existence of two types of noise effects. One is the READ-signal degradation just after the work-line rises. The other is the disturbance in sensing operation. The larger the ratio of the bit-line coupling capacitance to the other bit-line capacitance contributions the more serious both the noise effects are. These noise mechanisms can be explained by the charge conservation model and the simulation of sensing operation. A polycide bit-line structure is less susceptible to these noises than an Al bit line because its thickness and layer position. >

Advances in DRAM interfaces

New advanced architectures in DRAM interfaces seek to close the ever-widening performance gap between DRAM and microprocessor and to break the bandwidth bottleneck in graphics systems. We present an overview of five of these interfaces: EDO, SDRAM, RDRAM, CDRAM, and 3D-RAM. EDO will soon replace conventional DRAM, and SDRAM will partly take over in 66-MHz and higher frequency systems. Other interfaces will initially find target markets that exploit their unique features, and then seek wider market acceptance. Eventually, advances in DRAM will contribute to the trend toward a system on a chip.