Naohiro Suzuki

Fabrication of high aspect ratio doping region by using trench filling of epitaxial Si growth

A new trench filling epitaxial Si growth process has been proposed for the high aspect ratio doping region. This epitaxial process realizes the reducing void size in the trench compared with a conventional epitaxial process. The influence of the micro-void on multi-RESURF effect has been estimated by using numerical simulation. The decrease of breakdown voltage of simulated structures with micro-void that reflect experimental results is below 2.5% compared with ideal non-void structure.

Ultra low on-resistance Super 3D MOSFET

For the purpose of reducing the power MOSFET on-resistance in the range of under 300V breakdown voltage, we have already proposed a new power MOSFET hat we call the Super 3D MOSFET. At 70V breakdown voltage, the simulated total specific on-resistance was 19 m/spl Omega/-mm/sup 2/ and below the R/sub on/ Si limit. In this work, we present the structural design for source and drain resistance in order to utilize the widened channel and drift path effectively. And also we mention the manufacturing influence of the in-depth distribution such as gate oxide thickness and doping concentration of drift layer to reduce the specific on-resistance. Furthermore, we will present the experimental results concerning the on-resistance reduction by deepening the structure.

Break-through of the trade-off between on-resistance and ESD endurance in LDMOS

For the purpose of high ESD endurance and low on-resistance in LDMOS, we propose a new trench gate LDMOS. We call this structure HST-LDMOS (hard snapback trench gate LDMOS). In order to improve ESD endurance and on-resistance, the HST-LDMOS has P/sup +/ region between the driftN/sup -/ and N/sup +/ source and trench gate. Simulation results show that the HST-LDMOS achieves the ESD endurance of 16kV/mm/sup 2/ with the specific on-resistance of 6/spl square/6m/spl Omega/ mm/sup 2/. This is the best characteristic ever reported for the trade-off between on-resistance and ESD endurance. Furthermore, we presents the experimental on-resistance and snapback characteristics.