Jun-Seok Kim

A 1.25 ps Resolution 8b Cyclic TDC in 0.13

This paper describes the first implementation of the well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, an all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC is based on a 2 × time amplifier with an offset-compensated gain calibration scheme. The proposed cyclic TDC, fabricated in a 0.13 μm CMOS, shows a resolution of 1.25 ps with a total conversion range of ±160 ps, the maximum operating frequency of 100 MHz, and a power consumption of 4.3 mW at 50 MHz. The measured DNL and INL are ± 0.7 LSB and - 3 to + 1 LSB, respectively.

\mu

This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, an on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An asynchronous clocking scheme realizes pipeline operation for higher throughput. The TDC was implemented in standard 0.13-μm CMOS technology and has a maximum throughput of 300 MS/s and a resolution of 1.76 ps with a total conversion range of 1.8 ns. The measured DNL and INL were 0.6 LSB and 1.9 LSB, respectively.

m CMOS

This paper proposes a high-efficiency two-stage three-level grid-connected photovoltaic (PV) inverter. The proposed two-stage inverter comprises a three-level step-up converter and a three-level inverter. The three-level step-up converter not only improves the power-conversion efficiency by lowering the voltage stress but also guarantees the balancing of the dc-link capacitor voltages using a simple control algorithm; it also enables the proposed inverter to satisfy the VDE 0126-1-1 standard of leakage current. The three-level inverter minimizes the overall power losses with zero reverse-recovery loss. Furthermore, it reduces harmonic distortion, the voltage ratings of the semiconductor device, and the electromagnetic interference by using a three-level circuit configuration; it also enables the use of small and low-cost filters. To control the grid current effectively, we have used a feed-forward nominal voltage compensator with a mode selector; this compensator improves the control environment by presetting the operating point. The proposed high-efficiency two-stage three-level grid-connected PV inverter overcomes the low efficiency problem of conventional two-stage inverters, and it provides high-power quality with maximum efficiency of 97.4%. Using a 3-kW prototype of the inverter, we have evaluated the performance of the model and proved its feasibility.

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS

We report a VGA dynamic vision sensor (DVS) with a 9µm pixel, developed through a digital as well as an analog implementation. DVS systems in the literature try to increase spatial resolution up to QVGA [1–2] and data rates up to 50 million events per second (Meps) (self-acknowledged) [3], but they are still inadequate for high-performance applications such as gesture recognition, drones, automotive, etc. Moreover, the smallest reported pixel of 18.5µm is too large for economical mass production [3]. This paper reports a 640×480 VGA-resolution DVS system with a 9µm pixel pitch supporting a data rate of 300Meps for sufficient event transfer in spite of higher resolution. Maintaining acceptable pixel performance, the pixel circuitry is carefully designed and optimized using a BSI CIS process. To acquire data (i.e., pixel events) at high speed even with high resolution (e.g., VGA), a fully synthesized word-serial group address-event representation (G-AER) is implemented, which handles massive events in parallel by binding neighboring 8 pixels into a group. In addition, a 10b programmable bias generator dedicated to a DVS system provides easy controllability of pixel biases and event thresholds.

High-Efficiency Two-Stage Three-Level Grid-Connected Photovoltaic Inverter

A high-efficiency bridgeless three-level power factor correction (PFC) rectifier is proposed. The circuit configuration of the proposed rectifier consists of four metal oxide semiconductor field-effect transistor (MOSFET) switches, and the reverse recovery problems of the switches are eliminated. Also, the proposed rectifier with three voltage levels reduces the power losses, harmonic components, voltage ratings, and electromagnetic interference. To control the grid current and the output voltage effectively, a feed-forward nominal voltage compensator with the mode selector is developed; by presetting the operating point of the grid voltage, this compensator improves the control environment. Thus, the proposed three-level PFC rectifier with developed control algorithm provides high power quality and high efficiency of 99.05%. Experimental results based on a 1-kW prototype are provided to evaluate its performance and verify the analysis.

4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation

This study proposes a bidirectional grid-connected single-power-conversion converter with low-input battery voltage. The proposed bidirectional converter consists of a bidirectional dc–dc converter and an unfolding bridge, and the power conversion stage only corresponds to a bidirectional dc–dc converter. The bidirectional dc-dc converter can perform bidirectional power conversion between the low input battery voltage and a rectified sine wave due to its step-up/down voltage regulation functions. The unfolding bridge unfolds the rectified sine wave into the grid voltage and provides a current path to the grid. The study also proposes a control algorithm to regulate the grid current through a single power-processing stage. The control algorithm is comprised of a feed-forward nominal voltage compensator and a repetitive control scheme. The feed-forward nominal voltage compensator presets the operating point to lighten the burden of the grid current control, and the repetitive controller provides precise control of the grid current. Thus, the proposed bidirectional grid-connected single-power-conversion converter results in high power quality and high efficiency. Experimental results based on a 250-W prototype module are conducted to evaluate the performance of the converter and to verify the analysis.

High-Efficiency Bridgeless Three-Level Power Factor Correction Rectifier

We propose a novel method for identifying and classifying motions that offers significantly reduced computational cost as compared to deep convolutional neural network systems with comparable performance. Our new approach is inspired by the information processing network architecture of biological visual processing systems, whereby spatial pyramid kernel features are efficiently extracted in real-time from temporally-differentiated image data. In this paper, we describe this new method and evaluate its performance with a hand motion gesture recognition task.

Bidirectional Grid-Connected Single-Power-Conversion Converter With Low-Input Battery Voltage

Fast and efficient motion estimation is essential for a number of applications including the gesture-based user interface (UI) for portable devices like smart phones. In this paper, we propose a highly efficient method that can estimate four degree of freedom (DOF) motional components of a moving object based on an event-based vision sensor, the dynamic vision sensor (DVS). The proposed method finds informative events occurred at edges and estimates their velocities for global motion analysis. We will also describe a novel method to correct the aperture problem in the motion estimation.

Computationally efficient, real-time motion recognition based on bio-inspired visual and cognitive processing.

Common mode voltage generated by PWM switching causes motor bearing failures in inverter-motor drive systems, since bearing current runs through parasitic capacitances and motor bearings to ground. In this paper, we propose a method of reducing bearing current with the use of an embedded circular comb-like coil in the stator slots. We verified the validity of the proposed method by simulation and experiment.