Yunjae Suh

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18

The resolution of multi-bit linear TDC is closely related to process technology since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference between two inverter delays, a large number of inverter stages is required to cover a large detection range, resulting in long conversion time and high power consumption. Well-established data-conversion architectures have also been sought to achieve both large detection range and high resolution [4,5]. The two-step TDC was proposed to improve both the resolution and detectable range by amplifying the time residue after the coarse conversion for the fine conversion [4]. But, the previous time amplification schemes [4, 6] use metastability and suffer from small input range and gain uncertainties due to nonlinearity and PVT variations. This paper presents a power-efficient and wide dynamic range sub-exponent TDC. Based on a cascaded chain of 2× time amplifiers, the TDC generates the exponent-only information for the fractional time difference.

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This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, an on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An asynchronous clocking scheme realizes pipeline operation for higher throughput. The TDC was implemented in standard 0.13-μm CMOS technology and has a maximum throughput of 300 MS/s and a resolution of 1.76 ps with a total conversion range of 1.8 ns. The measured DNL and INL were 0.6 LSB and 1.9 LSB, respectively.

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This paper presents a 1-GHz ΔΣ fractional-N PLL with a noise-filtering scheme using a FIR-embedded phase interpolator. The proposed dual-referenced interpolation scheme compensates for systematic nonlinearity in circuit operation and increases immunity to mismatches in input seed phases. By multiple use of a dual-referenced interpolator, the phase interpolator realizes an embedded FIR filtering for the quantization noise from the ΔΣ modulator. The implemented PLL in 0.13- μm CMOS consumes 16.8 mW and shows a reduction of the phase noise by 34 dB. With 3.2-MHz-wide bandwidth, the proposed filtering technique achieves an in-band noise of -106 dBc at 100 kHz and an out-of-band noise of -107.5 dBc at 6 MHz.

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS

In the design of a fractional-N PLL, the trade-off between in-band VCO noise and ΔΣ quantization noise constrains the choice of loop bandwidth. Various circuit schemes have been proposed to relax such constrains with noise canceling methods [1, 2] at the cost of significant extra power and chip area, and with FIR filtering techniques [3, 4] utilizing multiple charge pumps (CPs), PFDs and dividers. To reduce the ΔΣ quantization noise, fractional phase rotation [4] has been also a popular approach as an alternative to the dual modulus divider. However, high-resolution phase interpolators (PIs) suffer from nonlinearities due to random mismatches among phase steps and systematic imperfections in circuit operation when the interpolated vector approaches quadrant boundaries, and such nonlinearities eventually limit the amount of noise reduction in PI-based PLL. This work presents a 1GHz ΔΣ fractional-N PLL based on the noise filtering by FIR-embedded PI. The proposed PI scheme greatly improves phase linearity by a dual-referenced interpolation and realizes FIR filtering without using multiple CPs, PFDs, and dividers. The designed fractional-N PLL shows a comparable phase-noise performance to that of an integer-N PLL even with loop bandwidth of 0.1×fref.

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC). The amplifier performs a class-AB operation by smoothly changing between a comparator-like semidigital driver and a continuous-time high-gain amplifier according to the input voltage difference. A 10-bit pipelined ADC with 2.5-bit/stage architecture is implemented in a 0.13- CMOS. The ADC consumes 1.25 mW at a sampling rate of 25 MS/s and achieves a Nyquist-rate figure-of-merit of 139 and 232 fJ/c-s without and with power consumption from a resistor ladder, respectively.

A 0.1-f ref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering

This paper presents a low-power resistive sensor interface circuit with correlated double sampling which reduces the effect of amplifier offset and enables time-interleaved single-to-differential sampling. The proposed sampling scheme, used with a 12b SAR-type analog-to-digital converter, effectively doubles the input signal and improves linearity. The fabricated chip in 0.13μm CMOS demonstrates a sampling rate of 1-kS/s and a dynamic range of 117dB with a maximum conversion error of 0.32-percent while consuming only 11.3-μW from single supply voltage of 0.5V.

A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier

A 8 GByte/s single-ended parallel transceiver is implemented in a 0.18 mum standard CMOS with a current-balanced pseudo-differential signaling for high-speed memory interface. With a segmented group-inversion coding, 16-bit data is encoded to 20 pins for dramatic reduction of simultaneous switching noise which has been a bottleneck in high-speed parallel links. The proposed pseudo-differential signaling achieves a power-efficient current-mode parallel termination with a reduction of driving current of about 40-percent. For the termination, virtual voltage sources are self-generated by tracking the center of eye opening. The transceiver shows a BER of less than 10-12 at 4 Gb/s/pin.

A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling

We propose a novel method for identifying and classifying motions that offers significantly reduced computational cost as compared to deep convolutional neural network systems with comparable performance. Our new approach is inspired by the information processing network architecture of biological visual processing systems, whereby spatial pyramid kernel features are efficiently extracted in real-time from temporally-differentiated image data. In this paper, we describe this new method and evaluate its performance with a hand motion gesture recognition task.

A 8 GByte/s transceiver with current-balanced pseudo-differential signaling for memory interface

This paper presents an energy-efficient 10-b pipelined ADC with a current-mode amplifier. The proposed amplifier achieves high gain, low static power consumption and supply voltage scalability without any calibration or timing control. The fabricated ADC in 65-nm CMOS process achieves FOMs of 14.3-to-36.9 fJ/c-s with a supply voltage range from 0.6-V to 1.0-V.

Computationally efficient, real-time motion recognition based on bio-inspired visual and cognitive processing.

A transistor-based background on-chip self-calibration technique is proposed to obtain PVT-independent circuit parameters. With little implementation complexity, the proposed direct I-V calibration of performance determining transistors efficiently achieves stable operation of precision circuits. As an example application to a design of a PLL, the calibration scheme adjusts critical parameters such as VCO gain and charge-pump current to achieve adaptive bandwidth characteristics. The PLL, implemented in a 0.18 mum CMOS, shows a wide lock-range of 10 MHz-1 GHz with the rms jitter of 5.7 ps at 1 GHz.