Jun Su Lee

Optical and Electronic Packaging Processes for Silicon Photonic Systems

Fiber optic interconnection processes and hybrid integration of electronic devices for high speed Si photonic systems are presented. Thermal effects arising from these hybrid integration processes are also investigated. An overview of ePIXfab which offers affordable access to an advanced Si photonic foundry service is also presented. This includes the presentation of fundamental photonic packaging design rules which can greatly reduce the time and cost associated with the development of complex Si photonic devices.

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver

Silicon photonics (SiPh) has been identified as a prime technology targeting cost-effective short-range optical links [1]. Wavelength-division multiplexing (WDM) is an attractive approach for enabling high aggregate transceiver bandwidth without increasing the number of optical fibers used in the link. Ring-based optical modulators and wavelength-selective filters are attractive devices for scalable WDM SiPh transceivers owing to their compact footprint and moderate power required for thermal tuning. In this paper, we report on a thermally controlled ring-based flip-chip integrated CMOS-SiPh transceiver with 4 channels operating at 20Gb/s.

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonic-packaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

Flip Chip Packaging of Digital Silicon Photonics MEMS Switch for Cloud Computing and Data Centre

We report on the flip chip packaging of Micro-Electro-Mechanical System (MEMS)-based digital silicon photonic switching device and the characterization results of 12 × 12 switching ports. The challenges in packaging N² electrical and 2N optical interconnections are addressed with single-layer electrical redistribution lines of 25 <italic>μ</italic>m line width and space on aluminum nitride interposer and 13° polished 64-channel lidless fiber array (FA) with a pitch of 127 <italic>μ</italic>m. 50 <italic>μ</italic>m diameter solder spheres are laser-jetted onto the electrical bond pads surrounded by suspended MEMS actuators on the device before fluxless flip-chip bonding. A lidless FA is finally coupled near-vertically onto the device gratings using a 6-degree-of-freedom (6-DOF) alignment system. Fiber-to-grating coupler loss of 4.25 dB/facet, 10^–11 bit error rate (BER) through the longest optical path, and 0.4 <italic>μ</italic>s switch reconfiguration time have been demonstrated using 10 Gb/s Ethernet data stream.

Optical and electronic packaging process for silicon photonic systems

Fibre optic interconnection processes and hybrid integration of electronic devices for high-speed Si photonic systems are presented. An overview of ePIXfab which offers affordable access to an advanced Si photonic foundry service is also presented.

Hybrid integration of VCSELs onto a silicon photonic platform for biosensing application

This paper presents a technology of hybrid integration vertical cavity surface emitting lasers (VCSELs) directly on silicon photonics chip. By controlling the reflow of the solder balls used for electrical and mechanical bonding, the VCSELs were bonded at 10 degree to achieve the optimum angle-of-incidence to the planar grating coupler through vision based flip-chip techniques. The 1 dB discrepancy between optical loss values of flip-chip passive assembly and active alignment confirmed that the general purpose of the flip-chip design concept is achieved. This hybrid approach of integrating a miniaturized light source on chip opens the possibly of highly compact sensor system, which enable future portable and wearable diagnostics devices.

Thermal challenges for packaging integrated photonic devices

In this work, we present thermal imaging and analysis of a silicon photonic optical network unit (ONU) for next generation passive optical networks (NG-PONs). A high-speed thermal camera is used to capture both the dynamic and steady-state temperatures of the photonic integrated circuit (PIC) and electric integrated circuit (EIC) at the core of the ONU. The dynamic temperature measurements of the PIC and EIC on powering-up the ONU show several distinct “steps” before the steady-state temperature is reached, and we show that these features can be predicted and fitted using a simple lumped-element rate-equation model. Steady-state temperature measurements made by mounting the ONU module on a thermally-stabilized stage allow the coefficient of performance (COP) of the thermoelectric cooler (TEC) in the module to be evaluated for simulated ambient temperatures ranging from 15-45 °C. This provides valuable information on the operational cost of the ONU in the field, where temperature-stabilization of the PIC represents a significant fraction of the overall power-budget.

Packaging of 50 × 50 MEMS-actuated silicon photonics switching device

We report on the packaging of the 50 × 50 MEMS-actuated silicon photonics switching device through flip-chip assembly and a lidless 64-channel fibre array polished at 13° angle. The device, measuring 10 mm × 10 mm, contains more than 2500 bond pads with a dimension of 65 μm × 65 μm, with the actuating MEMS structures locating 15 μm away at 4 sides of each bond pads. An average switching voltage of 35 V recorded at package level complies with data recorded during device probing while fibre-to-grating coupler loss was measured to be 4.25dB / facet at around 1550nm.