Carmelo Scarcella

Optical and Electronic Packaging Processes for Silicon Photonic Systems

Fiber optic interconnection processes and hybrid integration of electronic devices for high speed Si photonic systems are presented. Thermal effects arising from these hybrid integration processes are also investigated. An overview of ePIXfab which offers affordable access to an advanced Si photonic foundry service is also presented. This includes the presentation of fundamental photonic packaging design rules which can greatly reduce the time and cost associated with the development of complex Si photonic devices.

Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonic-packaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links

We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZMs Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMECs ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only.

A 20Gbaud/s PAM-4 65nm CMOS optical receiver using 3D solenoid based bandwidth enhancement

This paper presents an optical receiver (RX) suitable for amplifying a high-speed PAM-4 signal. To achieve a high gain-bandwidth product at low power consumption, a triple inductively peaked regulated cascode (RGC) transimpedance amplifier is used. The inductors are implemented as small 3D solenoids to reduce chip area and optimized for minimum group delay variation. The receiver further includes a Cherry Hooper variable gain amplifier, a continuous time linear equalizer and a 50Ω differential buffer, and achieves a gain of 65 dBΩ at 14 GHz bandwidth. The chip was fabricated using a 65nm CMOS technology and integrated with an 80fF Germanium photodiode by a microbump flip-chip process onto a Silicon Photonic chip. The input referred noise current density is 23.4 pA/VHz. Clear eye diagrams up to 20Gbaud/s (40Gbit/s) have been measured. At this baud rate, the RXs power consumption is 80mW, corresponding to an energy efficiency of 2pJ/bit.