Nicola Pavarelli

Optical and Electronic Packaging Processes for Silicon Photonic Systems

Fiber optic interconnection processes and hybrid integration of electronic devices for high speed Si photonic systems are presented. Thermal effects arising from these hybrid integration processes are also investigated. An overview of ePIXfab which offers affordable access to an advanced Si photonic foundry service is also presented. This includes the presentation of fundamental photonic packaging design rules which can greatly reduce the time and cost associated with the development of complex Si photonic devices.

Packaged hybrid III-V/silicon SOA

We present a hybrid III-V/silicon SOA, mounted in a planar package, with a fiber-to-fiber gain up to 10 dB, maximum internal gain of 28±2 dB, an internal noise figure of 10-11 dB and an output saturation power around 9 dBm.

22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver

Silicon photonics (SiPh) has been identified as a prime technology targeting cost-effective short-range optical links [1]. Wavelength-division multiplexing (WDM) is an attractive approach for enabling high aggregate transceiver bandwidth without increasing the number of optical fibers used in the link. Ring-based optical modulators and wavelength-selective filters are attractive devices for scalable WDM SiPh transceivers owing to their compact footprint and moderate power required for thermal tuning. In this paper, we report on a thermally controlled ring-based flip-chip integrated CMOS-SiPh transceiver with 4 channels operating at 20Gb/s.

Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonic-packaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

Hybrid III-V/Silicon SOA in Optical Network Based on Advanced Modulation Formats

A hybrid III-V/silicon semiconductor optical amplifier (SOA) is presented, which shows a maximum fiber-to-fiber gain of 10 dB and a maximum internal gain around 28 ± 2 dB. The device was fabricated from III-V material wafer-bonded onto a silicon-on-insulator wafer. The optical mode transfers between silicon and III-V waveguides by means of waveguide tapers. Vertical grating couplers are used to connect the SOA to optical fibers. The device was packaged and tested in a transmission experiment. In a loop configuration containing 25 km of single-mode fiber, the SOA amplifies data signals of various modulation formats. Transmission with a bit error rate below the forward error correction limit is demonstrated for up to ten loops using QPSK, six loop using 8QAM, and four loops using 16QAM.

Packaging challenges for integrated silicon photonic circuits

Cost-effective packaging of silicon photonic devices presents a significant bottleneck to commercialization of the technology. One way of addressing this packaging challenge is to use techniques that have been developed by the electronics industry and which also benefit from the use of advanced electronics assembly equipment. Even packaging processes such as fiber coupling can benefit from this approach, along with the hybrid integration of devices such as electronic components (e.g. modulator driver integrated circuits). In this paper, we will present developments made by our group towards achieving scalable fiber and electronic packaging processes that rely on electronic assembly techniques such as flip-chip assembly. We will also provide an overview of packaged prototypes being developed within our group for telecom and sensing applications and how these packaging technologies are now being made available to users through the ePIXfab foundry service.

InGaAs Surface Normal Photodiode for 2

High bandwidth 2-μm wavelength surface normal p-i-n photodiodes using a high indium-content InGaAs strain-relaxed absorbing layer clad by p- and n-doped AlInGaAs layers are realized. A parabolic grading was used to relax the lattice constant from that of the InP substrate. We compare structures with different p-doping profiles and absorber thicknesses to achieve a 3-dB bandwidth of ~10 GHz while maintaining a photoresponsivity of 0.93 A/W. A clear opening of the 10-Gb/s eye pattern was obtained with an input power of -3.07 dBm. By temperature-control of the mesa passivation process, the device leakage was reduced to 0.52 μA at -5 V bias.

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Fibre optic interconnection processes and hybrid integration of electronic devices for high-speed Si photonic systems are presented. An overview of ePIXfab which offers affordable access to an advanced Si photonic foundry service is also presented.