Jung Hoon Oh

Modeling and Design Methodology of High-Efficiency Class-F and Class-

In this paper, efficiency-limiting physical constraint effects imposed on the knee voltage, along with a variation of the optimum load resistance, are investigated for highly efficient Class-F and Class- amplifiers. First, for an accurate analysis and comparison, new current waveform models are identified, and a realistic approach incorporated using a nonzero knee voltage and voltage-dependent nonlinear capacitance is employed to derive the voltage waveforms of the amplifiers. An analysis is performed to show the efficiency, output power, power gain, and output power compression points for both modes. Using this knowledge, along with a complete performance comparison, we provide a direction for optimizing the amplifier design. The analytic results are further verified based on the measured results of 3.54-GHz Class-F and Class- amplifiers using a commercial 60-W peak-to-envelope power gallium-nitride device. The experimental results show that Class-F and Class- amplifiers operate at drain efficiencies of 69.9% and 69.4% at saturated output powers of 47.4 and 47.2 dBm, respectively. These remarkably similar performances have excellent agreement with the predicted analysis at our operational frequency.

{\hbox{F}}^{{\hbox{-}1}}

In this paper, a high-efficiency envelope-tracking (ET) transmitter incorporating a novel efficiency-boosting function is proposed and implemented. An inverse Class-F power amplifier is utilized and optimized using the proposed output loading condition, which enhances its efficiency at the high probability region. This matching network can be conveniently implemented by controlling the nonlinear capacitance of the power transistor. For an accurate analysis, the output waveforms are modeled in terms of the nonlinear capacitance, and the efficiency and output power are subsequently analyzed and successfully optimized. For a high-efficiency envelope amplifier (EA), we propose a new EA utilizing a 2-bit switching stage in place of a 1-bit switching stage. This proposed architecture effectively reduces the ripple current, improving the efficiency of the EA. To verify our analysis, we have fully implemented a 3.54-GHz high-efficiency ET transmitter including a digital processing block. The experimental results show that the ET transmitter using a commercial 60-W peak-envelope-power GaN device operates at a drain efficiency of 44% and power-added efficiency of 39.6% with a gain of 10.1 dB at an average output power of 40 dBm for a 10-MHz third-generation long-term evolution signal with 8.5-dB peak-to-average power ratio. Using a digital pre-distortion function, the adjacent channel leakage ratio is less than -47.5 dBc.

Power Amplifiers

This paper presents a 1.5 bit (3-level) envelope amplifier to improve the overall efficiency of wideband high linearity envelope tracking power amplifier. The proposed envelope amplifier has been devised with two switches providing the different supply voltages. Since the unnecessary current (ripple current) induced by a switching stage can be reduced by the multi-level quantization, the efficiency of a proposed envelope amplifier is 5% higher compared with that of a conventional architecture. With the proposed envelope amplifier, we have designed and implemented the 3.54GHz high efficiency envelope tracking power amplifier using a commercial 60W PEP GaN device. The efficiency boosting effect is further verified by the measured results. The experiment results show that the envelope tracking power amplifier operates at drain efficiency (DE) of 43.6% and power added efficiency (PAE) of 39.2% and a gain of 10.1dB at average output power of 40 dBm for a 10MHz WiMAX signal with 8.5 dB peak-to-average power ratio (PAPR). By using digital predistortion function, the adjacent channel leakage ratio (ACLR) is less than −45.4dBc at 20MHz offset.