Jung Hyuk Koh

Electric field induced polarization and strain of Bi-based ceramic composites

The ferroelectric properties and strain behaviors of 0-3-type-ceramic composites were investigated. (100-x)Bi0.5(Na0.75K0.25)TiO3-xBiAlO3 (x = 5, 6, and 7: abbreviated as 95BNKT-5BA, 94BNKT-6BA, and 93BNKT-7BA, respectively, and the three compositions are altogether designated as BNKT-BA) were chosen as a matrix materials, and ferroelectric Bi0.5Na0.5TiO3 (f-BNT), Bi0.5(Na0.8K0.2)0.5TiO3 (f-BNKT), and 98.5Bi0.5(Na0.8K0.2)0.5TiO3-1.5BiAlO3 (f-BNKTBA) grains as inclusions. Large f-BNT, f-BNKT, and f-BNKTBA grains strongly affect the ferroelectric properties and strain behaviors of the BNKT-BA matrix in the composite. In 95BNKT-5BA with f-BNT and f-BNKT, negative strain was observed, indicating that the ferroelectric phase is formed and stabilized. 93BNKT-7BA with f-BNT, f-BNKT and f-BNKTBA showed an increase in positive strain, which is associated with low field-induced phase transition. It was found from the strain curve that two contributions, ferroelectric phase stabilization and phase transition activat...

High-Temperature Stable Operation of Nanoribbon Field-Effect Transistors

We experimentally demonstrated that nanoribbon field-effect transistors can be used for stable high-temperature applications. The on-current level of the nanoribbon FETs decreases at elevated temperatures due to the degradation of the electron mobility. We propose two methods of compensating for the variation of the current level with the temperature in the range of 25–150°C, involving the application of a suitable (1) positive or (2) negative substrate bias. These two methods were compared by two-dimensional numerical simulations. Although both approaches show constant on-state current saturation characteristics over the proposed temperature range, the latter shows an improvement in the off-state control of up to five orders of magnitude (−5.2 × 10−6).

Influence of plasma-etch damage on the interface states in SOI structures investigated by capacitance?voltage measurements and simulations

Au/SiO2/n-Si metal-oxide-silicon-on-insulator (MOSOI) capacitors were fabricated to study the damage caused by reactive ion etching (RIE) on (1 1 0) oriented silicon-on-insulator (SOI) substrates. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance–voltage (C–V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measurements revealed that C–V curves significantly change and a negative voltage shift occurs for plasma-damaged capacitors. The simulated band diagram profiles and potential distribution of the corresponding structures indicate that the C–V shift is mainly due to the removal of a parasitic depletion capacitance (Cp) in the substrate, when the interface charges (Qf) are present at the gate oxide/SOI interface. For etch-damaged MOSOI samples, the surface roughness and the interface charges (Qf) have been found to increase by ~1.94 × 1012 cm−2 with respect to the reference devices, whereas the increase was reduced for sacrificial-oxidation treated samples, which implies a recovery from the plasma-induced etch damage on SOI structures.

Process dependent output characteristics of resonant cavity type avalanche photodetector

In this work, we proposed resonant cavity (RC) type avalanche photodetector (APD) as one technical breakthrough in their wavelength performance and integration with surface light emitting devices for further applications. InAs self-assembled quantum dots (SAQDs) were used as absorbing layer for the 1 /spl mu/m light absorption and AlAs/GaAs quarter-wavelength DBRs were used to construct resonant cavity. Optimized epitaxial layer and device structures were calculated by impact ionization model and also the device fabrication processes were calibrated.