Jung-Sheng Chen

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

A new sub-1V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic NPN and PNP BJT devices in the CMOS process, is presented. The new proposed sub-1V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25 /spl mu/m CMOS process. The experimental results have verified that, at the minimum supply voltage of 0.9 V, the output reference voltage is 536.7 mV with a temperature coefficient of 19.55 ppm//spl deg/C from 0/spl deg/C to 100/spl deg/C. With 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz.

New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation

A new sub-1-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-1-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-mum CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5 ppm/degC from 0 degC to 100 degC. With a 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz

Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process

The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the dc stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, are measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability in the operational amplifier can be improved by the stacked configuration under small-signal input and output application. The impact of soft and hard gate-oxide breakdowns on operational amplifiers with two-stage and folded-cascode structures has been analyzed and discussed. The hard breakdown has more serious impact on the operational amplifier.

New Gate-Bias Voltage-Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process

A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-mum LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.

Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process

The effects of the gate-oxide reliability of MOSFETs on operational amplifiers were investigated with two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The tested operating conditions include unity-gain buffer (close-loop configuration) and comparator (open-loop configuration) under different input frequencies and signals. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, were measured to verify the impact of gate-oxide reliability on circuit performance of the operational amplifier. The gate-oxide reliability can be improved by the stacked configuration in the operational amplifier with folded-cascode structure. A simple equivalent device model of gate-oxide reliability for CMOS devices in analog circuits was investigated and simulated.

Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device

A new sub-1-V CMOS bandgap voltage reference without using low threshold voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25 /spl mu/m CMOS process. The experimental results show that, at the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV with an effective temperature coefficient of 58.1 ppm//spl deg/C while DC current is 28 /spl mu/A. At 0.85 V supply voltage, the measured power noise rejection ratio is -33.2 dB at 10 KHz.

The Impact of Gate-Oxide Breakdown on Common-Source Amplifiers With Diode-Connected Active Load in Low-Voltage CMOS Processes

The influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the nonstacked and stacked structures under analog application in a 130-nm low-voltage CMOS process. The test conditions of this work include the dc stress, ac stress with dc offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as small-signal gain, unity-gain frequency, phase margin, and output dc voltage levels, are measured to verify the impact of gate-oxide reliability on circuit performances of the common-source amplifiers with diode-connected active load. The small-signal parameters of the common-source amplifier with the nonstacked diode-connected active-load structure are strongly degraded than that with the stacked diode-connected active-load structure due to a gate-oxide breakdown under analog and digital applications. The common-source amplifiers with diode-connected active load are not functionally operational under digital application due to the gate-oxide breakdown. The impact of soft and hard gate-oxide breakdowns on the common-source amplifiers with nonstacked and stacked diode-connected active-load structures has been analyzed and discussed. The hard breakdown has more serious impact on the common-source amplifiers with diode-connected active load.

SLOPE: a test pattern generator based on stop line oriented path end algorithm

The authors present a test pattern generator, SLOPE, based on the stop line oriented path end algorithm, for combinational digital circuits. It combines the advantages of FAN and FAST by utilizing a controllability measure and observability measure to assist guessing in the test generation process. With some strategies adopted in the algorithm, it generates tests with fewer number of backtrackings. Benchmark circuits run with SLOPE show that it outperforms PODEM and FAN for most circuits.<<ETX>>

Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.