Junhua Shen

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

Successive-approximation ADCs (SARs) have excelled in two spaces: in very-high-SNR applications where the precision and stability of capacitors are leveraged along with the use of large signal swings and in high-speed, low-resolution applications in which the SARs low power and simplicity has enabled high levels of time-interleaving. In between, ADCs with greater than 10 effective bits and sample rates above 20MS/s are typically not based on the SAR architecture. The sequential nature of the SAR algorithm makes it difficult to achieve both high speed and high accuracy, as increasing the resolution requires each bit decision to be both faster and lower noise. This paper presents a SAR that overcomes some of the conventional speed limitations; it uses a 1.2V-only supply and achieves >70dB SNDR at 80MS/s, which extends the state of the art while maintaining comparable FoM.

Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC

This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17

A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS

\mu \text{W}

Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC

, the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator’s energy efficiency.

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

This paper presents a SAR ADC that is much smaller and faster than the recently reported precision (16-bit and beyond) SAR ADCs [1, 2, 3]. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference switching using reservoir capacitors to improve speed and reduce area, LSB repeats and ADC residue measurement to improve efficiency. The prototype achieves 97.5dB SFDR while operating at 16MS/s and consumes 16.3mW. It was fabricated in 55nm CMOS and occupies 0.55mm2.

A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS

This paper presents a new energy-efficient ring oscillator collapse-based comparator, which is called edge-pursuit comparator (EPC) and demonstrated it in a 15-bit SAR ADC. The comparator automatically adjusts the performance according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. The employed SAR ADC supplements a 10-bit differential main CDAC with a 5-bit common-mode CDAC which uses common to differential gain tuning to improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40nm CMOS shows 74.12 dB SNDR and 173.4 dB FOMs. The comparator consumes 104 nW with the full ADC consuming 1.17 μW.

SELF-TIMED DIGITAL-TO-ANALOG CONVERTER

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference using reservoir capacitors to improve speed and reduce area, plus LSB repeats and statistical residue measurement to improve efficiency. The prototype achieves 97.5-dB spurious-free dynamic range at 100-kHz input while operating at 16 MS/s and consumes 16.3 mW. It was fabricated in a 55-nm CMOS process and occupies 0.55 mm2.

Background calibration of ADC reference voltage due to input signal dependency

This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed unique ADC architecture and calibration technique addresses the issue of signal dependent reference voltage droop during SAR ADC bit trials and orthogonalize the bit weights to achieve 16bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the bit cap, the first reported in this type of SAR ADC. Measurement result from a prototype test chip shows +/−0.8 LSB (16-bit level) INL at 1MSPS.