Lalinda D. Fernando

A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS

This paper presents a SAR ADC that is much smaller and faster than the recently reported precision (16-bit and beyond) SAR ADCs [1, 2, 3]. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference switching using reservoir capacitors to improve speed and reduce area, LSB repeats and ADC residue measurement to improve efficiency. The prototype achieves 97.5dB SFDR while operating at 16MS/s and consumes 16.3mW. It was fabricated in 55nm CMOS and occupies 0.55mm2.

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference using reservoir capacitors to improve speed and reduce area, plus LSB repeats and statistical residue measurement to improve efficiency. The prototype achieves 97.5-dB spurious-free dynamic range at 100-kHz input while operating at 16 MS/s and consumes 16.3 mW. It was fabricated in a 55-nm CMOS process and occupies 0.55 mm2.

A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS

This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed unique ADC architecture and calibration technique addresses the issue of signal dependent reference voltage droop during SAR ADC bit trials and orthogonalize the bit weights to achieve 16bit linearity. In addition, the proposed architecture maximizes SNR by sampling on to the bit cap, the first reported in this type of SAR ADC. Measurement result from a prototype test chip shows +/−0.8 LSB (16-bit level) INL at 1MSPS.