Junichi Mitsuhashi

Mechanism of negative‐bias temperature instability in polycrystalline‐silicon thin film transistors

It is found that 0.1 V‐order threshold voltage shift (Vth shift) takes place in polycrystalline‐silicon thin film transistors during negative‐bias temperature stress (−BT stress), while the Vth shift in the case of positive‐bias temperature stress is negligibly small. The Vth shift caused by −BT stress has an exponential dependence on the stress gate bias and reciprocal of temperature. Moreover, it also has a close relation with the grain size of poly‐Si films and the hydrogenation process. However, it is independent of the gate insulator materials. Some models previously proposed for amorphous silicon TFTs could not explain these results. A new model is proposed based on a reaction between hydrogen and the SiO2 network at and near the poly‐Si/SiO2 interface to clarify the mechanism and for consistent interpretation of the experimental results. Furthermore, the model has been verified qualitatively.

Si/SiO2 interface states and neutral oxide traps induced by surface microroughness

Silicon‐surface microroughness was formed by cleaning cycles of an NH4OH‐H2O2‐H2O solution. Not only the roughness of the silicon surface, but also the roughness of the thermally oxidized surface and that of the surface after the removal of the thermal oxide (corresponding to the Si/SiO2 interface roughness) were observed by means of atomic‐force microscopy. By using metal‐oxide‐semiconductor structured samples, investigations were conducted of the electrical properties induced by surface microroughness, such as the oxide‐trapped charges, Si/SiO2 interface states, neutral oxide‐trap centers, and oxide‐breakdown characteristics. As a result, it was clarified that the neutral oxide traps, as well as the Si/SiO2‐interface states, apparently increase in spite of only a small change in roughness. It was also verified, however, that the oxide‐trapped charges and the oxide breakdown do not change over the scale of roughness change in the present experiments, if contaminants were carefully eliminated from the Si ...

Effect of P-SiN Passivation Layer on Time-Dependent Dielectric Breakdown in SiO2

Effects of hydrogen and mechanical stress due to a plasma deposited SiN passivation layer on time-dependent dielectric breakdown were investigated, and it is found that the p-SiN layer degrades the TDDB characteristics concerned with interface state and trap generation. The native trap density remarkably increases with annealing MOS capacitors encapsulated by p-SiN layer. The degradation of interface state, which is induced by the electron injections, is enhanced on the devices with p-SiN layer by annealing. These degradations are mainly caused by the diffusion of atomic hydrogen to the SiO2-Si interface. The atomic hydrogen is considered to be released from the N-H bond in p-SiN layer by annealing. Large mechanical stress, up to 5~8 × 109 dyne/cm2, due to p-SiN layer also introduces the degradation of TDDB characteristics in a random failure region.

Electron beam testing of VLSI circuits assisted by focused ion beam etching

Abstract Electron beam testing assisted by focused ion beam etching was examined. Before electron beam testing (EB testing), a small window was made in the passivation film by focused ion beam etching (FIB etching). EB testing was performed through this window. This method was useful because charge buildup on the passivation film is avoided during EB testing. The threshold voltage shift caused by FIB etching was permitted until the residual film thickness on the gate electrode became 0.5μm. This technique was applied to measure the internal voltage waveform of the 256K bit dynamic RAM and confirmed that it was effective for functional testing and failure analysis of VLSI circuits.

Study of Time Dependent Dielectric Breakdown Distribution in Ultrathin Gate Oxide

The computer simulations of the time dependent dielectric breakdown (TDDB) percolation path are performed for ultrathin gate oxides. With our new percolation model, an interesting and new behavior of TDDB distribution was found. Weibull slope decreases monotonously with decreasing oxide thickness, and has a gap at an oxide thickness of approximately the effective defect size. This behavior can be understood well if we consider that an overlap of two neighboring defects becomes necessary to cause a sudden breakdown when oxide thickness exceeds the effective defect size. This phenomenon is very important because Weibull slope has a large effect on device reliability.

Evaluation of hot carrier effects in TFT by emission microscopy

Hot carrier degradation of p-channel polycrystalline silicon thin film transistors was investigated by emission microscopy. An automatic measurement system was developed for the evaluation of hot carrier degradation. In the system, the measurement of electrical characteristics and the monitoring of photoemission are done simultaneously. This system was used to identify the dominant mechanism of hot carrier degradation in thin-film transistors and to evaluate the effect of plasma hydrogenation on hot carrier degradation.<<ETX>>

Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs)

Wafer-level time dependent junction degradation (TDJD) is investigated as a technique for evaluating junction reliability. The TDJD phenomenon due to latent defects is revealed by high constant voltage stressing, in the same way that the TDDB test determines the long-term reliability of the junction. Latent defects enhance the junction degradation due to TDJD. Electrons trapped at the perimeter of a junction degrade junction characteristics. Although the perimeter of a junction is composed with local oxidation of silicon (LOCOS) and/or gate edge, the gate edge is found to be more significant for the TDJD characteristics.<<ETX>>

Nitride thickness dependence of trap generation and negative stress-induced current in oxidized nitride films (<5 nm)

Abstract The trap generation and negative stress-induced current in oxidized nitride films for two film thickness values have been investigated using MIS capacitors and p-channel MISFET transistors. It was already observed that in thin nitride film the gate current is two orders of magnitude larger than that for the thick film. But for a constant top oxide on the nitride films, the gate current was almost the same. After subjecting both films to a constant current stress, the gate current measured for the oxidized thick nitride film was larger than that of the oxidized thin nitride film. The hole and electron currents were measured independently before and after stress application. The current increase in oxidized thin nitride film is caused by the stress-induced generation of trapped electrons, while the current increase in the oxidized thick nitride film is caused by the stress-induced generation of trapped holes in the top-oxide film and in the bulk nitride.

Improved reliability of wet oxidized nitride MOS capacitors in comparison to RTP N2O oxidized nitride films

Abstract A nitride film has been oxidized in a wet (O:H = 8:1) ambient or N 2 O atmosphere at different temperatures and times and the electrical characteristics have been studied. It was found that the reliability of MOS capacitors with a wet oxidized nitride film is better than that of N 2 O oxidized nitride film grown (1100°C, 30 s) samples. In addition it was found that the TDDB characteristics are improved with an increase of the N 2 O oxidation temperature and time. The improvement of the MOS capacitors with a wet oxidized nitride film can be attributed to the more efficient replacement of excess Si atoms and H-related species such as SiH bonds, which makes the ON layer more resistive and with less trap sites than the N 2 O oxidized nitride film.