Junko Komori

Effects of N distribution on charge trapping and TDDB characteristics of N/sub 2/O annealed wet oxide

Wet pyrogenic oxide of different thicknesses was annealed in N/sub 2/O ambient and the N concentration in the films was studied by using SIMS (secondary ion mass spectroscopy). It was found that for a certain annealing time and temperature, the N concentration (at %) increases with decreasing wet oxide thickness and the location of the peak of N is observed near the interface of nitrided oxide and Si substrate. On the contrary, after nitridation the concentration of H is higher in the thicker wet oxide of thickness 100 /spl Aring/ and also does not change much from the surface to the interface. For the thinner wet oxide of thickness 40 /spl Aring/, the concentration of H is less and decreases toward the interface. Gate dielectrics were characterized using high-frequency and quasi-static measurements. After a constant current stress, a large distortion was observed for the N/sub 2/O annealed wet oxide of 98 /spl Aring/ whereas for the N/sub 2/O annealed wet oxide of 51 /spl Aring/ the distortion was small. With increasing stressing time, hole trap is followed by electron trapping for the wet oxide of 98 /spl Aring/ whereas for the N/sub 2/O annealed wet oxide of 51 /spl Aring/, hole trapping increases a little at the beginning and then saturates. From the TDDB characteristics, a longer t/sub BD/ was observed for N/sub 2/O annealed wet oxide of 51 /spl Aring/ compared to 98 /spl Aring/. From the experimental results, it can be suggested that the improved reliability of thin gate oxide is due to the large amount of N concentration near the interface only. Hence for the device fabrication process, if the wet oxide is nitrided in N/sub 2/O ambient, the reliability of gate oxide will be improved in the ultrathin region.

Detection of defects in metal interconnects by the nonbias-optical beam induced current technique

The mechanism for detecting defects by the nonbias-optical beam induced current technique is clarified by examining images and conducting simulations. This technique, using an electromotive current as a result of optical laser irradiation with no application of voltage, is very useful for analysis of metal interconnect failure in ultra large scale integrated devices. The characteristic images obtained by this technique, consisting of pairs of bright and dark regions, reveal point defects, such as voids in metal stripes and vias. It is found, by examining the characteristic images of defects, that the electromotive current generated near the defects originates as a result of the thermoelectromotive effect. Furthermore, it is confirmed by thermal simulations and transient current simulations, that the asymmetric temperature profiles near the defects generate the electromotive current and show the characteristic images.

Three-Dimensional Visualization Technique for Crystal Defects in High Performance p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Embedded SiGe Source/Drain

We have performed a detailed analysis of crystal defects in high-performance p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) with embedded SiGe source/drain (S/D), using low-angle annular dark field (ADF) scanning transmission electron microscopy (STEM) and electron tomography. We achieved successful results in three-dimensional visualization of crystal defects for the first time. Consequently, we have discussed about the three-dimensional physical geometric relationship between crystal defects and device architecture. This approach is sure to contribute to the development of advanced complementary metal–oxide–semiconductor (CMOS) devices using strained silicon technology.

Locally delineating of junctions and defects by local cross-section electron-beam-induced-current technique

Abstract The local cross-section electron-beam-induced-current (EBIC) technique together with a focused ion beam (FIB) for cross-sectional viewing is discussed. The cross-section formed by FIB treatment on the ultra-large scale integrated (ULSI) device surface maintains sufficient electrical insulation between every node (including the PN junction). This was confirmed in advance using a test structure and an actual ULSI chip. High-resolution EBIC images could be obtained for some samples by irradiating a low-energy electron beam onto the FIB cross-section. This local cross-sectional EBIC technique is very useful for delineating PN junctions and pointing out defect portions upon the failure of ULSI devices. Furthermore, we found that the floating well, which was not connected to the outside electrode, was visualized by thinning the back (∼1 μm) of the cross-section with a FIB. It was clarified by electromotive current simulations that this phenomenon originates in the change in potential of the well due to the staying of the generated carriers which could not diffuse. This application is also very useful for the delineation of multiple well structures in ULSI devices.

Mechanism of pre-annealing effect on electromigration immunity of Al–Cu line

Abstract In this work, we have investigated effects of pre-annealing, which means annealing performed prior to electromigration (EM) test, on EM lifetime of Al–Cu lines. We also investigated the relationships between void formation and size of Cu precipitated area in the line under various pre-annealing conditions. It is found that EM lifetime decreases while the size of the Cu precipitated area increases with lengthening of the pre-annealing period. However, no void is observed after this pre-annealing treatment. The results indicate that the tiny voids generated by formation of Cu precipitation do not move during the pre-annealing period. In the case of EM testing, Cu precipitation occurs followed by void formation at the cathode area, probably due to diffusion of vacancies which are generated by Cu atom movement by electron wind. As a result, resistance of the line increases and eventually it fails completely. It is demonstrated that pre-annealing helps Cu atoms to accumulate at the grain boundary forming the Cu precipitates. However, in samples with no pre-annealing treatment, the accumulation of Cu atoms at the grain boundaries begins just after the start of the EM testing and then the Cu precipitates diffuse toward the anode. Since EM test conditions are the same for samples with and without pre-annealing treatment, the only variation is the incubation time to accumulate Cu atoms at the grain boundaries. This is the reason why EM lifetime of pre-annealed samples is shorter than that of samples with no pre-annealing treatment.

A new test structure for evaluation of extrinsic oxide breakdown

A new test structure for evaluation of extrinsic oxide breakdown is proposed. The active gate area which is needed to predict reliability is shown. By using this new test structure, activation energies for not only the intrinsic breakdown but also for the extrinsic breakdown are obtained.

Evaluation of Silicide Morphology by Near-Infrared-Laser Optical-Beam-Induced-Current Technique

We found that the near-infrared-laser optical-beam-induced-current (IR-OBIC) technique was very useful for the evaluation of silicide morphology in ultralarge-scale integrated (ULSI) devices. By this technique, it is possible to detect the cohesion points of silicide as two-dimensional images by scanning a near-infrared laser from the back of the chip. The cohesion points appear as bright spots. We confirmed that the number and intensity of bright spots changed according to the extent of cohesion for some different samples upon varying the silicide layer thickness or thermal treatment time after silicide formation. Furthermore, other experiments were performed to clarify the image formation mechanism at cohesion points. It was demonstrated that the electromotive current was generated upon irradiation by the near-infrared-laser, and Schottky junctions were formed at cohesion points. Thus, it was clarified that the images obtained at cohesion points by this technique are a result of the electromotive current generated due to the carriers (electrons or holes) that are excited over the Schottky barrier formed at cohesion points. The IR-OBIC technique can be used to detect the silicide morphology nondestructively without the need to remove the upper layers of the silicide layer. This study reveals a novel application of the IR-OBIC method which is a very useful technique for the evolution of the self-aligned silicide (SALICIDE) process or structure in future ULSIs.

Evaluation of hot carrier effects in TFT by emission microscopy

Hot carrier degradation of p-channel polycrystalline silicon thin film transistors was investigated by emission microscopy. An automatic measurement system was developed for the evaluation of hot carrier degradation. In the system, the measurement of electrical characteristics and the monitoring of photoemission are done simultaneously. This system was used to identify the dominant mechanism of hot carrier degradation in thin-film transistors and to evaluate the effect of plasma hydrogenation on hot carrier degradation.<<ETX>>

Junction evaluation by time dependent degradation due to high constant voltage stressing (DRAMs)

Wafer-level time dependent junction degradation (TDJD) is investigated as a technique for evaluating junction reliability. The TDJD phenomenon due to latent defects is revealed by high constant voltage stressing, in the same way that the TDDB test determines the long-term reliability of the junction. Latent defects enhance the junction degradation due to TDJD. Electrons trapped at the perimeter of a junction degrade junction characteristics. Although the perimeter of a junction is composed with local oxidation of silicon (LOCOS) and/or gate edge, the gate edge is found to be more significant for the TDJD characteristics.<<ETX>>

Oxide thickness dependence of nitridation effects on TDDB characteristics

Using wet oxide thickness ranging from /spl sim/50 to 80 /spl Aring/, effects of nitridation on time-dependent dielectric breakdown (TDDB) characteristics have been investigated. Results show that capacitors with nitrided oxide have shorter t/sub bd/ up to a thickness of /spl sim/60 /spl Aring/ but turnaround behaviour was found for /spl sim/50 /spl Aring/ nitrided oxide. It is suggested that the turnaround behaviour of t/sub bd/ of nitrided wet oxide of /spl sim/50 /spl Aring/ compared to the wet oxide seems to be due to the greater nitrogen concentration at the interface than for thick wet oxide of over 60 /spl Aring/ for the same nitridation conditions.