Takayuki Matsukawa

Monte Carlo Calculations on Electron Scattering in a Solid Target

The Monte Carlo technique using a simple single scattering model, different from Reimers, is applied to the field of the Electron Probe Microanalyzer (EPMA) and the Scanning Electron Microscope (SEM). The calculations show fairly good agreement with the experiments on back-scattered electrons, energy dissipation, characteristic X-ray production and secondary electron emission. Also the electron trajectories are depicted on the chart by the plotter connected with the digital computer.

Titanium silicidation by halogen lamp annealing

Silicidation of titanium (Ti) thin films sputter‐deposited onto silicon (Si) was performed by the halogen lamp annealing method. This method was found to be quite effective in forming oxide‐free and homogeneous titanium disilicide (TiSi2). Temperature dependence of silicidation was investigated by using Rutherford backscattering spectroscopy, x‐ray diffraction, and sheet resistance measurements. It was found that the dominant crystal phase of silicide formed during annealing at 600 and 625 °C for 90 sec was titanium monosilicide (TiSi), and that a homogeneous TiSi2 with resistivity of ∼15 μΩ cm was formed at 700 °C. Self‐aligned TiSi2 with low resistivity can be obtained with two‐step annealing: the first‐step annealing was carried out below 600 °C and followed by removal of unreacted Ti on silicon dioxide (SiO2), and the second‐step annealing was carried out above 650 °C.

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V/sub th/ lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V/sub th/ lowering at 0.4- mu m gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4- mu m gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4- mu m gate length. >

A 90ns 1Mb DRAM with multi-bit test mode

A 1Mb DRAM using a half Vcc biased memory cell with a reduced electric field of 2MV/cm will be reported. A shared sense amplifier design and a continous nibble mode are also included. Additionally, a test pin allows testing as a 256K×4 memory. Die is 65mm2.

Simultaneous formation of TiN and TiSi2 by lamp annealing in NH3 ambient and its application to diffusion barriers

The dependence of TiN/TiSi2 bilayer formation on Si by lamp annealing of Ti upon annealing temperature, ambients, and impurity in Si was investigated. In NH3 ambient, nitridation ratio on undoped Si at 680 and 800 °C is 40% and 25%, respectively. When annealing is performed in N2, the nitridation ratio of Ti is only about 25% at both 680 and 800 °C. The above dependence of nitridation ratio on annealing ambient is due to the difference in decomposition energy of gas molecules. The nitridation ratio increases on arsenic‐implanted Si because of a retardation effect of the arsenic on the silicidation reaction. The bilayer formation process was applied to the AlSi contact metallization on the n+ diffused layer. From measurements on electrical characteristics of the AlSi/TiN/TiSi2/n+ Si contact system, the following results were obtained: (1) Contact resisitivity is 3.5–5.3×10−7 Ω cm2. (2) The TiN/TiSi2 contact electrode is thermally stable against Al. In particular, when the bilayer is formed in NH3 at compar...

A reliable 1-Mbit DRAM with a multi-bit-test mode

A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.

A 90ns 4Mb DRAM in a 300 mil DIP

A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.

A 4-Mbit DRAM with folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell

A 5-V 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b dynamic RAM with a static column model and fast page mode has been built in a 0.8-/spl mu/m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10.9 /spl mu/m/SUP 2/ and requires only a 2-/spl mu/m trench to obtain a storage capacitor of 50 fF with 10-nm SiO/SUB 2/ equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C/SUB B/-to-C/SUB S/ capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300-mil dual-in-line package with performances of 90-ns RAS access time and 30-ns column address access time.

A high density 4M DRAM process using folded bitline adaptive side-wall isolated capacitor (FASIC) cell

Submicron CMOS process technologies for a high density 4M DRAM are presented emphasizing a cell area reduction to 10.9 um2 using a newly proposed FASIC cell. Two novel techniques were developed to realize the new cell structure. The oblique ion implantation technique can make a shallow impurity doping into the side wall and the local oxidation at the side wall technique makes the half-contact/cell architecture on the peripheral trench type cell.

Effect of P-SiN Passivation Layer on Time-Dependent Dielectric Breakdown in SiO2

Effects of hydrogen and mechanical stress due to a plasma deposited SiN passivation layer on time-dependent dielectric breakdown were investigated, and it is found that the p-SiN layer degrades the TDDB characteristics concerned with interface state and trap generation. The native trap density remarkably increases with annealing MOS capacitors encapsulated by p-SiN layer. The degradation of interface state, which is induced by the electron injections, is enhanced on the devices with p-SiN layer by annealing. These degradations are mainly caused by the diffusion of atomic hydrogen to the SiO2-Si interface. The atomic hydrogen is considered to be released from the N-H bond in p-SiN layer by annealing. Large mechanical stress, up to 5~8 × 109 dyne/cm2, due to p-SiN layer also introduces the degradation of TDDB characteristics in a random failure region.