Junichi Sakano

A novel high-conductivity IGBT (HiGT) with a short circuit capability

This paper presents a new high-conductivity IGBT (HiGT) with a DMOS structure and an n-type hole-barrier layer surrounding a p-layer. The hole-barrier layer acts as a barrier to prevent the holes from flowing into the p-layer and stores them in the n-layer. The HiGT provides a collector-emitter saturation voltage (V/sub CE(sat)/) of about 1 V lower than that of the conventional IGBT, while it maintains a high blocking voltage of 3.3 kV by controlling the carrier concentration of the hole-barrier layer. The HiGT has tough short circuit capability of more than 10 /spl mu/s at 125/spl deg/C with a saturation current similar to that of the conventional IGBT.

A Trench-Gate High-Conductivity IGBT (HiGT) With Short-Circuit Capability

This paper describes a new 600-V trench-gate high-conductivity insulated gate bipolar transistor (trench HiGT) that has both a low collector-emitter saturation voltage of 1.55 V at 200 and a tough short-circuit capability of more than 10 . The trench HiGT also has better tradeoff relationship between turn-off switching loss and collector-emitter saturation voltage compared to either an insulated gate bipolar transistor (IGBT) with a planar gate or a conventional trench gate. A reverse transfer capacitance that is 50% lower than that of the planar-gate IGBT and an input capacitance that is 40% lower than that of a conventional trench gate IGBT have been obtained for the trench HiGT.

A Planar-Gate High-Conductivity IGBT (HiGT) With Hole-Barrier Layer

A high-conductivity insulated gate bipolar transistor (IGBT) (HiGT) with a double diffused MOS structure and an n-type hole-barrier layer surrounding a p-layer (planar HiGT) is presented. The hole-barrier layer prevents the holes from flowing into the p-layer and stores them in the n-layer. The planar HiGT provides a better tradeoff between collector-emitter saturation voltage [VcE(sat)] and turn-off loss than conventional IGBTs, regardless of the injection efficiency of the p-layer on the collector side, while it maintains a high blocking voltage by controlling the sheet carrier concentration of the hole-barrier layer. The planar HiGT has a tough short-circuit capability of more than 10 mus at 125degC, with a saturation current similar to that of conventional IGBTs.

High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm2 was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.

600V single chip inverter IC with new SOI technology

A 600V three-phase single chip inverter IC has been developed using a new SOI technology instead of conventional 500V Dielectric Isolation (DI) technology. In this new technology, 600V high voltage devices were materialized with a newly introduced poly-Si field plate and a multi diffusion region in order to reduce the electric field. A new IGBT accomplishes high current density with an on-resistance of 1.8Ωmm2 by using a multi emitter structure and an n-type well layer that reduces JFET resistance between emitter channels. Moreover, a thin Si layer and universal contact structure for fast extraction of excess carriers contribute to low switching losses. The turn-off energy loss of the IGBT is 54% of that of a conventional one at 135°C. The developed inverter IC has a maximum output voltage of 600V and a maximum output current 1A. Compared to the conventional 500V IC, the operational power consumption is reduced from 2.6W to 2.3W.

3.3 kV punchthrough IGBT with low loss and fast switching

This paper presents a new punchthrough (PT) IGBT with a high blocking voltage of 3.3 kV. We numerically show that a high injection efficiency with a p+layer and local lifetime control in an n-layer are more effective in reducing the turn-on and turn-off losses, respectively. A p+epitaxial layer at the collector has been made in order to realize a high injection efficiency, which greatly reduced the turn-on loss, experimentally. When a local lifetime control technique is applied to this new PT IGBT, the turn-off loss is decreased by approximately 50% compared to a conventional PT IGBT with uniform lifetime control of electron irradiation. The new PT IGBT provides fast switching with rise and fall times of about 1 /spl mu/s at 125/spl deg/C. In addition, in this PT IGBT it is easy to apply a high resistivity n-layer without increasing its thickness or losing high blocking voltage in comparison with non-punchthrough (NPT) IGBT, which can get low failure rate (FIT) with cosmic ray.

Novel 600-V trench high-conductivity IGBT (Trench HiGT) with short-circuit capability

This paper describes new 600-V trench high-conductivity IGBTs (trench HiGTs) that have lower on-state voltages of 1.42 and 1.55 V at 200 A/cm/sup 2/ and tough short-circuit capabilities of 5 and 10 /spl mu/s, respectively. These HiGT have a better trade-off between turn-off losses and on-state voltages than conventional trench IGBTs, even better than planar IGBTs. They also offer a lower reverse transfer capacitances (-50%) than the planar IGBT. The input capacitance obtained were lower (-30% to -60%) than that of a conventional trench IGBT.

A New 80V 32x32ch Low Loss Multiplexer LSI for a 3D Ultrasound Imaging System

This paper presents a new concept for an 80V multiplexer LSI with the worlds largest 32 times 32ch cross-point switches for a real-time 3D ultrasound imaging system. This system requires hundreds of thousands of high voltage electrical switches. We propose a new gate floating type analog switch circuit with thin gate oxide power MOSFETs and a low-loss gate driving method for this LSI. The developed LSI can handle plusmn40V at 15 MHz ultrasound signal with reasonably low power dissipation (10mW/LSI) and can operate at a 33 MHz clock frequency for the first scanning operation. The developed LSIs are assembled in a hand probe and show a fine 3D volume image

3D ultrasound imaging system using Fresnel ring array & high voltage multiplexer IC

In a previous report (Satoshi Tamano et al, Proc. IEEE Ultrason. Symp., p.1310-1313, 2003), a prototype 2D convex-convex shaped array probe and a real-time 3D ultrasound imaging prototype system was reported. This time, our convex-convex (40 mmR-40 mmR, 3.5 MHz center frequency) shaped 2D array probe is modified to include approximately 8,000 PZTs. Moreover, the scale of our custom multiplexer IC is enlarged from 8:1 with 8 channels to 32:1 with 32 channels. These high voltage multiplexer ICs are chip-on-board (COB) mounted on a PCB inside the 2D array probe. With this improved probe and multiplexer ICs, it is possible to bundle more than 3,000 active PZTs into 32 Fresnel rings. It is expected that our system will enable us to form a uniform beam in a 3D space by use of the Fresnel ring and to bundle a large number of PZTs into 32 to 64 channels.

High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology

We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.