Shinji Shirakawa

High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm2 was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.

High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology

We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.