Masahiro Iwamura

CMOS/bipolar circuits for 60-MHz digital processing

High-performance bipolar/CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 4-GHz cutoff frequency is combined with standard CMOS devices on the same chip, has been applied to a processor. The design strategy was to provide high integration density using the CMOS circuit and accelerate the critical paths using the Hi-BiCMOS circuits. Hi-BiCMOS circuits with low-voltage swing have been developed and applied to a 32-bit arithmetic logic unit and a 128-kb ROM with bipolar drivers to drive a heavy load capacitance. A 17-ns 32-bit carry propagation delay time and a 17-ns ROM access cycle time have been achieved using 2-/spl mu/m Hi-BiCMOS technology. A minicomputer CPU with a 60-MHz machine cycle can be implemented with these circuits.

1.3- mu m CMOS/bipolar standard cell library for VLSI computers

The CMOS/bipolar standard cell library has been enhanced from 2 to 1.3 mu m for application to VLSI computers, such as 32-bit supermini- and microcomputers. This library has macrocells such as a 256-kb/8.4-ns ROM, 32-bit/4.5-ns carry propagation circuits for a 32-bit ALU, 4-kbyte/17-ns cache memory including an address translation function, and a 64-bit/37-ns multiplier. High integration density is obtained by using CMOS-based circuits and fast operation is achieved by using CMOS/bipolar sense circuits and drivers. In the cache memory, a functional sense amplifier, in which a conventional sense amplifier and a comparator are merged, is used. How to combine CMOS and bipolar devices in the macrocells along with application of the library to the VLSI computers is discussed. >

A 6-ns 256-kbit BiCMOS TTL SRAM

A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<<ETX>>

A 6-ns 256-kb BiCMOS TTL SRAM

The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25 degrees C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a *8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm*10 mm. >

A high reliability and low loss 3-phase gate driver IC with a novel soft gate drive circuit for 42V motor generator system

We have developed a three-phase driver IC for the 42V motor generator automotive system using a 100V class SOI isolated 0.5/spl mu/m three metal layer bipolar CMOS LDMOS process SOIPIC (SOI Intellectual Property Power IC). This IC has a soft gate drive function with a new concept of loss minimization for a low on-state-resistance 100V 500A class trench power MOSFET.

A BiCMOS 32-bit execution unit for 70 MHz VLSI computer

A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved

Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v

We describe new circuit techniques for an 8-11s ECL compatible 16Mb BiCMOS SRAM. This is the first reported implementation of ECL lOOK U0 compatibility with an operation voltage of less than 3.0V. We developed an ECL reference circuit that operates with a 2.3V supply voltage. A novel hierarchically divided common-emitter sense circuit reduces the delay due to long data lines to achieve a simulated address access time of 8ns under typical operating conditions.