Junichiro Yoshioka

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 /spl mu/m by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than /spl plusmn/0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260/spl deg/C in N/sub 2/ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150/spl deg/C for 1000 h in N/sub 2/ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs.

Processing, properties, and reliability of electroplated lead-free solder bumps

Eutectic tin-silver (Sn-Ag), tin-copper (Sn-Cu), and tin-silver-copper (Sn-Ag-Cu) solder alloys are potential lead-free materials for low-temperature processing of solder bumps on wafers. But, before they can be adopted to replace the existing lead-free materials, processes have to be developed to provide controls over composition, height and shape uniformity, and defect formation, such as micro-voids, which are detrimental to bump reliability. Over the last six years, we have developed an electroplating technology using a dip-plating machine for processing the three types of eutectic lead-free solder bumps on silicon wafer. Our process is suitable for mass production with well-controlled bump geometry and composition, and uniformity within 10% over the entire wafer. In this paper, we will describe our process and present our results on the bump properties, such as composition, melting point, and microstructure of the bumps.

Process development of electroplate bumping for ULSI flip chip technology

For flip-chip packaging applications, a fine pitch bump process on LSI wafers is required due to increased chip circuit density, operating speed, and performance. Plating process is suitable for making the fine pitch bumps with high-speed deposition and high reliability. At the same time, lead-free processes, for electronic devices and components, are required to address environmental concerns. Also, high-speed bumping processes have to be developed for mass production, low cost, small footprint, and high throughput. Ebara has developed electroplating technologies for eutectic Sn-Pb solder, high lead solder, lead-free solder, and copper stud bumps on silicon wafers with higher deposition rates. The bumps were fabricated as column or mushroom type using resist plating masks, such as negative, positive spin-on, and dry film photo resists. The results show that Ebaras processes are suitable for mass production, with well-controlled bump geometry.

Composition control for lead-free alloy electroplating on flip chip bumping

In lead-free alloy electroplating for Sn-Ag, Sn-Cu or Sn-Ag-Cu solder bumping, composition control is an important subject since the composition ratio is influential to the alloy structures and properties of the solders. The general assumption is that its very difficult to control the compositions of plated lead-free alloys in plating production lines because the composition ratio of the alloy element Ag or Cu is small and sensitive to the plating conditions in Sn base eutectic alloys. Also, when comparing with Sn-Pb solder, the larger electric potential difference between the components of lead-free alloys will make the composition ratio of plated alloys unstable in electroplating. Good bump height uniformity is not the only requirement for the integration process. It is also important to attain well-controlled compositional uniformity of lead-free solder. Therefore, it is important to control the electric potential distribution, metal ion concentrations, and their concentration ratios in the plating solution near the plating surface. In bump plating production lines, there are also other factors influencing the plated solder compositions including plating rate, plating solution flow, anode, and substrate pattern conditions. This paper describes our study of the factors affecting the control of the compositions in the lead-free alloy plating processes. The composition control of lead-free solder bumping has been primarily experienced on 300mm wafers for flip chip or wafer level packaging. The results of this study show that an advanced electroplating process can be successfully applied to the fabrication of the lead-free solder bumps, and further, that it can be carried out with the present electroplating and reflow tools.