Tsuyoshi Tokuoka

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 /spl mu/m by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than /spl plusmn/0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260/spl deg/C in N/sub 2/ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150/spl deg/C for 1000 h in N/sub 2/ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs.