Junil Lee

REINVESTIGATION AND EXTENSION OF THE STEADY-STATE NYQUIST THEOREM FOR MULTI-TERMINAL SEMICONDUCTOR DEVICES AND ITS APPLICATION TO MINIMUM NOISE FIGURE IN MICROWAVE FIELD EFFECT TRANSISTORS

The steady‐state Nyquist theorem for multi‐terminal semiconductor devices, which describes the short‐circuit thermal noise currents in arbitrarily shaped multi‐terminal semiconductor devices, is reinvestigated. The concept of the equipotential surfaces for small ac signals is found to be wrong, which forces us to introduce a new approach to find the equipotential surfaces for noise voltages. Using this new approach, we rederive the steady‐state Nyquist theorem with the same results as in the previous derivation, and extend it to the hot carrier regime. Using the extended theorem, we express the minimum noise figure for microwave field effect transistors as a function of the measurable device parameters with no fitting constant. The derived minimum noise figure is shown to reduce to a simple form, which can also be used as an empirical relation with one fitting constant. This simple form can explain the experimental results very well in wide frequency ranges, and gives through a clear mathematical relation...

Interface states generated by heat treatment in Au/InGaP Schottky diodes

This work is a study of the formation of interface traps in Au/n−In0.5Ga0.5P contacts. The effects of heat treatment near the ohmic alloying temperature on the characteristics of the Schottky diodes are studied using current‐voltage (I‐V), capacitance‐voltage (C‐V), and deep level transient spectroscopy measurements. New interface states that are distributed around 0.73 eV below the conduction band minimum were generated by heat treatment above 350u2009°C before metallization. In a sample that was heat treated at 400u2009°C for 30 min, the maximum density of generated interface states was estimated to be approximately 2×1011 cm−2u2009eV−1. The origin of these interface states is attributed to the transformation of a phosphorus vacancy that is generated by the vaporization of phosphorus from the surface of In0.5Ga0.5P.

Steady‐state Nyquist theorem for multi‐terminal nondegenerate semiconductor devices

Formulas for the spectral intensities of the short‐circuit thermal noise currents in arbitrarily shaped multi‐terminal semiconductor devices under dc bias are derived by solving the Langevin‐type Boltzmann transport equations. The derived formulas are valid when the carrier distributions are not far from the local equilibrium distributions. Measurement data on short‐circuit thermal noise currents are obtained for a three‐terminal silicon bulk device. A comparison between the calculated and experimental results is made and thereby the validity of our theory is confirmed.

Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures

In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p+/n+ body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage (

Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

{V} _{D}

Analysis on temperature dependent current mechanism of tunnel field-effect transistors

)-induced lowering of the locally increased barrier and the increase of ambipolar current and too wide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration.

Theory of thermal noise in long-channel MOS transistors operating before saturation

A novel fabrication method is proposed to reduce large gate-to-drain capacitance (C GD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced C GD and positive shifted gate voltage (V G) versus C GD curves with the thicker GDOX.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure

In this paper, the total drain current (I D) of a tunnel FET (TFET) is decomposed into each current component with different origins to analyze the I D formation mechanisms of the TFET as a function of gate voltage (V GS). Transfer characteristics are firstly extracted with fabricated Silicon channel TFETs (Si TFETs) and silicon germanium channel TFETs (SiGe TFETs) at various temperatures. The subthreshold swings (SS) of both Si TFETs and SiGe TFETs get degraded and the SSs of SiGe TFETs get degraded more as temperature becomes higher. Then, all the I Ds measured at various temperatures are decomposed into each current component through technology computer aided design (TCAD) simulations with a good agreement with experimental data. As a result, it is revealed that Shockley–Read–Hall (SRH) recombination mainly contribute to the I D of a TFET before band to band tunneling (BTBT) occurs. Furthermore, the SS degradation by high temperature is explained successfully by the SRH recombination with electric field dependence.

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Abstract This article reports a reinvestigation of the existing thermal noise theory for long-channel MOS transistors, which is shown to have serious flaws as a thermal noise theory. We conclude that the spectral intensity of the channel thermal noise current for a long-channel MOSFET, operating before saturation at both strong and weak inversions, is best given by applying a new theory, which we refer to as the steady-state Nyquist theorem for one-dimensional devices. We also show that a general three-dimensional approach for calculation of the short-circuit thermal noise currents in semiconductor devices supports the new theory. Clear and definitive experimental evidence in support of the steady-state Nyquist theorem is provided.

MOSFET-TFET hybrid NAND/NOR configuration for improved AC switching performance

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (<8 ns) and a large on-off current ratio (>107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.