Ryoongbin Lee

Drift-Free pH Detection With Silicon Nanowire Field-Effect Transistors

The drift of drain current (ID) in silicon nanowire field-effect transistor sensors is analyzed under various conditions of pHs and liquid gate voltages (VLG). It is found that H+ penetration into Helmholtz layer or sensing insulator is the cause of the current drift. To suppress the drift, a novel and fast measurement method with a two-step VLG is proposed and demonstrated. The drift could be completely suppressed by controlling the duration of the first step pulse. The time required to remove the ID drift is significantly reduced by the proposed method, from ~1200 s to below 100 s on average.

Investigation of drift effect on silicon nanowire field effect transistor based pH sensor

It is widely accepted that the operation mechanism of pH-sensitive ion sensitive field effect transistor (ISFET) can be divided into three categories; reaction of surface sites, chemical modification of insulator surface, and ionic diffusion into the bulk of insulator. The first mechanism is considered as the main operation mechanism of pH sensors due to fast response, while the others with relatively slow responses disturb accurate pH detection. In this study, the slow responses (often called drift effects) are investigated in silicon nanowire (SiNW) pH-sensitive ISFETs. Based on the dependence on the channel type of SiNW, liquid gate bias, and pH, it is clearly revealed that the drift of n-type SiNW results from H+ diffusion into the insulator whereas that of p-type SiNW is caused by chemical modification (hydration) of the insulator.

Reduction method of gate-to-drain capacitance by oxide spacer formation in tunnel field-effect transistor with elevated drain

A novel fabrication method is proposed to reduce large gate-to-drain capacitance (C GD) and to improve AC switching characteristics in tunnel field-effect transistor (TFETs) with elevated drain (TFETED). In the proposed method, gate oxide at drain region (GDOX) is selectively formed through oxide deposition and spacer-etch process. Furthermore, the thicknesses of the GDOX are simply controlled by the amount of the oxide deposition and etch. Mixed-mode device and circuit technology computer aided design (TCAD) simulations are performed to verify the effects of the GDOX thickness on DC and AC switching characteristics of a TFETED inverter. As a result, it is found that AC switching characteristics such as output voltage pre-shoot and falling/rising delay are improved with nearly unchanged DC characteristics by thicker GDOX. This improvement is explained successfully by reduced C GD and positive shifted gate voltage (V G) versus C GD curves with the thicker GDOX.

Analysis on temperature dependent current mechanism of tunnel field-effect transistors

In this paper, the total drain current (I D) of a tunnel FET (TFET) is decomposed into each current component with different origins to analyze the I D formation mechanisms of the TFET as a function of gate voltage (V GS). Transfer characteristics are firstly extracted with fabricated Silicon channel TFETs (Si TFETs) and silicon germanium channel TFETs (SiGe TFETs) at various temperatures. The subthreshold swings (SS) of both Si TFETs and SiGe TFETs get degraded and the SSs of SiGe TFETs get degraded more as temperature becomes higher. Then, all the I Ds measured at various temperatures are decomposed into each current component through technology computer aided design (TCAD) simulations with a good agreement with experimental data. As a result, it is revealed that Shockley–Read–Hall (SRH) recombination mainly contribute to the I D of a TFET before band to band tunneling (BTBT) occurs. Furthermore, the SS degradation by high temperature is explained successfully by the SRH recombination with electric field dependence.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (<8 ns) and a large on-off current ratio (>107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

Nanowire size dependence on sensitivity of silicon nanowire field-effect transistor-based pH sensor

In this study, we investigated the effects of nanowire size on the current sensitivity of silicon nanowire (SiNW) ion-sensitive field-effect transistors (ISFETs). The changes in on-current (I on) and resistance according to pH were measured in fabricated SiNW ISFETs of various lengths and widths. As a result, it was revealed that the sensitivity expressed as relative I on change improves as the width decreases. Through technology computer-aided design (TCAD) simulation analysis, the width dependence on the relative I on change can be explained by the observation that the target molecules located at the edge region along the channel width have a stronger effect on the sensitivity as the SiNW width is reduced. Additionally, the length dependence on the sensitivity can be understood in terms of the resistance ratio of the fixed parasitic resistance, including source/drain resistance, to the varying channel resistance as a function of channel length.

MOSFET-TFET hybrid NAND/NOR configuration for improved AC switching performance

AC switching performances of Tunneling Field Effect Transistor (TFET) are investigated through mixed-mode TCAD simulations. Abnormal switching phenomena of TFETs are analyzed beyond the influence of low on-current (Ion) and large gate-to-drain capacitance (Cgd). Besides, hybrid NAND/NOR configurations are proposed to improve switching delay.