Atsushi Shimozato

Correlation between reliability of thermal oxides and dislocations in n-type 4H-SiC epitaxial wafers

The correlation between thermal oxide reliability and dislocations in n-type 4H-SiC (0001) epitaxial wafers has been investigated. The thermal oxides were grown by dry oxidation at 1200°C followed by nitrogen postoxidation annealing. Charge-to-breakdown values of thermal oxides decrease with an increase in the number of the dislocations in a gate-oxide-forming area. Two types of dielectric breakdown modes, edge breakdown and dislocation-related breakdown, were confirmed by Nomarski microscopy. In addition, it is revealed that basal plane dislocation is the most common cause of the dislocation-related breakdown mode.

Effects of interface state density on 4H-SiC n-channel field-effect mobility

We investigated the effects of D IT at the interface between SiO2 and Si-, C-, and a-face 4H-SiC in n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) that were subjected to dry/nitridation and pyrogenic/hydrotreatment processes. D IT at E C − E T = 0.2 eV was evaluated by the C − ψ S method using MOS capacitors and was accurately reflected in the subthreshold slope of the MOSFETs. The peak field-effect mobility was inversely proportional to D IT. The mobility for the a-face MOSFETs was 1.5 times or more higher than the other faces mobilities, indicating that mobility limiting factors other than D IT(0.2 eV) may exist for the Si- and C-face interfaces.

Relation between Defects on 4H-SiC Epitaxial Surface and Gate Oxide Reliability

Time-dependent dielectric breakdown (TDDB) measurement of MOS capacitors on an n-type 4 ° off-axis 4H-SiC(0001) wafer free from step-bunching showed specific breakdown in the Weibull distribution plots. By observing the as-grown SiC-epi wafer surface, two kinds of epitaxial surface defect, Trapezoid-shape and Bar-shape defects, were confirmed with confocal microscope. Charge to breakdown (Qbd) of MOS capacitors including an upstream line of these defects is almost the same value as that of a Wear-out breakdown region. On the other hand, the gate oxide breakdown of MOS capacitors occurred at a downstream line. It has revealed that specific part of these defects causes degradation of oxide reliability. Cross-sectional TEM images of MOS structure show that gate oxide thickness of MOS capacitor is non-uniform on the downstream line. Moreover, AFM observation of as-grown and oxidized SiC-epitaxial surfaces indicated that surface roughness of downstream line becomes 3-4 times larger than the as-grown one by oxidation process.

Effects of Dislocations on Reliability of Thermal Oxides Grown on n-Type 4H-SiC Wafer

The effects of dislocations in n-type 4H-SiC(0001) epitaxial wafers on the reliability of thermal oxides have been investigated. Charge-to-breakdown (QBD) values of thermal oxides decrease with increase in the dislocations under a gate-oxide area. Nomarski microscope observations show that dielectric breakdown of thermal oxides occurs at the position of dislocation in epitaxial layer. It is reavealed that basal plane dislocation is the most common cause of the dielectric breakdown.

N-channel field-effect mobility inversely proportional to the interface state density at the conduction band edges of SiO2/4H-SiC interfaces

We investigated the effects of the interface state density (D IT) at the interfaces between SiO2 and the Si-, C-, and a-faces of 4H-SiC in n-channel metal-oxide-semiconductor field-effect transistors that were subjected to dry/nitridation and pyrogenic/hydrotreatment processes. The interface state density over a very shallow range from the conduction band edge (0.00 eV < E C − E T) was evaluated on the basis of the subthreshold slope deterioration at low temperatures (11 K < T). The interface state density continued to increase toward E C, and D IT at E C was significantly higher than the value at the conventionally evaluated energies (E C − E T = 0.1–0.3 eV). The peak field-effect mobility at 300 K was clearly inversely proportional to D IT at 0.00 eV, regardless of the crystal faces and the oxidation/annealing processes.

Significant Improvement in Reliability of Thermal Oxide on 4H-SiC (0001) Face Using Ammonia Post-Oxidation Annealing

The effect of ammonia (NH3) post-oxidation annealing (POA) technique on the reliability of thermal oxides grown on a n-type 4H-SiC (0001) face by dry oxidation has been investigated. Comparing other POA techniques using hydrogen and nitrous oxide gases, it was indicated that the NH3 POA after dry oxidation remarkably improves the insulating properties of thermal oxides. The mode value of field-to-breakdown for thermal oxides prepared by NH3 POA was 12.1 MV/cm. The charge-to-breakdown (QBD) in the NH3 POA sample was the highest in all samples, and the QBD value at 63% cumulative failure rate was 19.1 C/cm2. In addition, the NH3 POA maintained excellent electron trapping characteristics of thermal oxides against the electron injection.

Evaluation of 4H-SiC Thermal Oxide Reliability Using Area-Scaling Method

The reliability of thermal oxides grown on an n-type 4H-SiC(0001) was investigated using an area-scaling method, and the influence of dislocation defects on the time-dependent dielectric breakdown characteristics of thermal oxides was examined. A thermal oxide was grown by dry oxidation at 1200 °C followed by nitrogen post-oxidation annealing. Using the area-scaling method, the time-to-breakdown (tBD) distribution curves of metal–oxide–semiconductor (MOS) capacitors with different gate area sizes were converged to a single one. It was clearly shown that origins of dielectric breakdown are edge breakdown and dislocation-related breakdown for steep and gradual slopes of the area-scaling normalized tBD distribution curve, respectively. In addition, a yield analysis of MOS capacitors quantitatively indicated that both threading screw dislocation and basal plane dislocation are predominant killer defects for the dielectric breakdown of thermal oxides on the 4H-SiC(0001) face.

Challenges of High-Performance and High-Reliablity in SiC MOS Structures

Influences of wafer-related defect and gate oxide fabrication process on MOS characteristics with gate oxides thermally grown on 4H-SiC (0001) wafer have been investigated for a realization of SiC MOS power devices. The SiC MOS characteristics depend on the gate oxide fabrication process, and are improved by the increase of DRY oxidation temperature and the applying of N2O and H2 POAs. In addition, it was clearly shown that predominant origins of SiC MOS reliability degradation are wafer-related defects such as dislocation and surface defects of epitaxial layer. Moreover, the planarization of SiC epitaxial layer surface using a CMP treatment is effective technique for the improvement of SiC MOS reliability.

Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment

This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

Influence of Processing and of Material Defects on the Electrical Characteristics of SiC-SBDs and SiC-MOSFETs

The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.