Juntaek Oh

A 77-GHz CMOS Power Amplifier With a Parallel Power Combiner Based on Transmission-Line Transformer

This paper presents a 77-GHz CMOS power amplifier (PA) with a parallel power combiner based on a transmission-line transformer (TLT). An inter-stage matched cascode power cell structure is applied to obtain high output power and efficiency, where a simple matching network between the common-gate and common-source stage is introduced. The parallel power combiner based on a broadside-coupled TLT is analyzed and compared with a series power combiner. The PA is fabricated using a 65-nm RF CMOS process. It achieves the saturated output power of 15.8 dBm, the power-added efficiency of 15.2%, and the power gain of 20.9 dB with a supply voltage of 2.0 V at 77 GHz.

A W-Band 4-GHz Bandwidth Phase-Modulated Pulse Compression Radar Transmitter in 65-nm CMOS

This paper presents a fully integrated W-band 4-GHz bandwidth (BW) pseudo-noise (PN)-coded pulse compression radar transmitter (TX) in a CMOS technology. The PN-coded pulse compression scheme is adopted to obtain high spectral density and to lower the TX leakage using a 63-bit PN code generator based on linear feedback shift registers. We propose a sub-harmonic pumped pulse former and a pulsed power amplifier for high TX efficiency with the suppression of local oscillator (LO)/2LO leakage. A frequency synthesizer including a frequency divider chain generates a sub-harmonic LO signal, as well as a 5-GHz digital clock. Digital blocks with the PN-code generator are synchronized with the clock signal, which makes all pulses start with the same phase. The proposed TX achieves 14.5-dBm maximum output power with the tuning range of 75-81.5 GHz, and the phase noise is -95.2 dBc/Hz at a 1-MHz offset in the range of LO frequencies. In pulse mode, it generates a 4-GHz BW RF pulse signal, which corresponds to a range resolution of 7.5 cm, and the average dc power dissipation is 160 mW.

A 79-GHz Adaptive-Gain and Low-Noise UWB Radar Receiver Front-End in 65-nm CMOS

A 79-GHz adaptive-gain and low-noise ultra-wideband radar receiver RF front-end integrated circuit in 65-nm CMOS is presented in this paper. The receiver consists of an adaptive-gain low-noise amplifier (AGLNA) and a g m-boosted sub-harmonic mixer (SHM). The proposed AGLNA controls the gain with adaptive biased circuits, which lowers the gain as the received signal power increases to provide wide dynamic range to the radar receiver without any external controls. We analyzed the input impedance of a cascode amplifier with a parallel resonant inductor, which improves the noise figure. The proposed g m-boosted SHM uses a transformer-based feedback network with NMOS bleeding circuits to provide a high conversion gain. The SHM was designed to use a differential local oscillator (LO) signal to have a simple structure and operate at low LO power. The measured conversion gain range was from 16 to -7.5 dB with a received power range from -45 to -5 dBm at 79.5 GHz. The measured noise figure was 10.5 dB and the measured 2LO-to-RF isolation was 70 dB. The chip area is 0.47×1.23 mm2.

A W-Band High-Efficiency CMOS Differential Current-Reused Frequency Doubler

A W-band differential frequency doubler using a current-reuse configuration in a 65 nm CMOS process is presented in this letter. The differential current-reuse circuit with a second harmonic coupling transformer is introduced to improve conversion gain at small input powers minimizing the effect of the RF bypass capacitor. The proposed circuit achieves a conversion gain of 0.8 ~ -4.2 dB and a fundamental rejection above 19 dB in the input frequency range of 36.5~44 GHz with -4 dBm input power. It has conversion gain variation below 1 dB when the input power varies from -7.4 to 0.1 dBm at 77 GHz. The dc power consumption is 14 mW. It has the highest conversion gain with the smallest chip size of 0.22 mm2 among all V-/W-band CMOS frequency doublers.

A 79 GHz g m -boosted sub-harmonic mixer with high conversion gain in 65nm CMOS

In this paper, a 79 GHz gm-boosted sub-harmonic mixer with high conversion gain is presented. As a gm-boosting technique, a transformer based feedback network with an NMOS bleeding path is proposed to achieve high conversion gain. The differential LO-driven sub-harmonic mixer has a simple structure and operates at low LO power. The measurement results show a conversion gain of 1.6 dB at a LO power of -5 dBm, a noise figure of 13 dB, and a 2LO-to-RF isolation of 38 dB. The power consumption of the sub-harmonic mixer is 12 mW. The circuit was fabricated using 65-nm CMOS technology with a chip area of 0.69×0.45 mm2.

A 77GHz CMOS medium power amplifier with transmission line transformers for multi-mode automotive radar system

A 77 GHz CMOS medium power amplifier (PA) with high efficient matching networks based on transformer is presented. The unit transistor size of a power cell is selected by analyzing its maximum available gain. The broadside-coupled Transmission-Line Transformers (TLTs) are implemented as matching networks for low insertion loss and wide band matching characteristics. The PA is fabricated using a 65-nm RF CMOS process. The saturated output power and the peak power-added efficiency at 76.5GHz is 12.8 dBm and 8%, respectively. The DC power consumption is 236 mW with a supply voltage of 2.0V.

Three-dimensional Visualization of Temperature Distribution using Optical Diffraction Tomography

We present a new approach to three-dimensional (3D) temperature distribution imaging using optical diffraction tomography (ODT). We reconstruct the 3D temperature distribution near gold nanorods under an illumination at their plasmonic resonance wavelength.

Millimeter wave UWB pulse radar front-end ICs

The 26 GHz and 79 GHz UWB frequency bands are used for short-range radar applications for automobile. In this paper, single chip front-end ICs for both frequency bands are presented. The pulsed oscillator at 26 GHz can produce UWB short pulses. It consumes power only during short duty cycles; thus, it allows a power-efficient radar. A stereo radar, which comprises two synchronized radars, is demonstrated with the ICs. Hybrid beam forming techniques based on base-band delay are also demonstrated. The pulsed front-end architecture of the proposed 79 GHz UWB pulse radar is discussed, which is expected to reduce power consumption. The performance of some circuit elements is also reported.