Junxia Ma

Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths

As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (i) during design validation to apply sufficient guardbands to critical paths and (ii) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure for maximizing power supply noise effects on critical paths while considering local voltage drop impacts is proposed. The proposed pattern generation and validation flow is implemented on the ITC’99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented in this paper. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed in the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practiced in industry.

Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test

Large switching during launch-to-capture cycle in delay test not only negatively impacts circuit performance causing overkill, but could also burn tester probes due to the excessive current they must drive. It is necessary to develop a quick and effective method to evaluate each pattern, identify high-power ones considering functional and tester probes’ current limit and make the final pattern set power-safe. Compared with previous low-power methods that deal with scan structure modification or pattern filling techniques, the new proposed method takes into account layout information and resistance in power distribution network and can identify peak current among C4 power bumps. Post-processing steps replace power-unsafe patterns with low-power ones. The final pattern set provides considerable peak current reduction while fault coverage is maintained.

Silicon evaluation of faster than at-speed transition delay tests

Researchers, based primarily on theoretical analysis of different coverage metric, have proposed the need to cover small delay defect (SDD). There is very little silicon data justifying the need to add SDD tests to the manufacturing flow. This paper attempts to fill this gap. A high volume manufacturing experiment to ascertain the added screening capability of defective parts and infant mortality of FAST_TDF tests are described. Quantitative silicon data are presented.

A novel method for fast identification of peak current during test

Existing commercial power sign-off tools analyze the functional mode of operation for a small time window. The detailed analysis used makes such tools impractical in determining test peak power where a large amount of scan shift cycles have to be analyzed. This paper proposes an approximate test peak power analysis flow capable of computing test peak power at each power bump in the design. The flow uses physical design information, like power grid, power bump location, packaging information, along with the design netlist. We present correlation studies, on industrial design, and show the proposed flow to correlate within 5%of the accurate commercial power sign-off tool. In addition, we demonstrate that this flow, unlike the commercial power sign-off tool, can process a very large number of transition delay tests in a reasonable time.

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric

Power supply noise and crosstalk are considered as the two major noise sources that negatively impact signal integrity in digital integrated circuits. In this paper, we propose a novel quality metric to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. The proposed procedure quickly selects the best set of patterns for testing the critical paths under power supply noise and crosstalk effects. It also offers the design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. Simulation results demonstrate that the patterns selected by the proposed methodology generate the worst-case supply noise and crosstalk effects on target paths.

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Power supply noise and crosstalk are the two major noise sources that are pattern dependent and negatively impact signal integrity in digital integrated circuits. These noise sources play a greater role in sub-65nm technologies and may cause timing failures and reliability problems in a design; thus must be carefully taken into consideration during test pattern generation and validation. In this paper, we propose a novel method to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. It quantifies the noises with a pattern quality value (Q) using the activated aggressor gates and nets information. The proposed method offers design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. By evaluating the failed test pattern, the proposed method can be used to help identify the root cause during failure analysis. Simulation results demonstrate the efficiency and effectiveness of the pattern grading procedure.

Background on VLSI Testing

As technology feature size of devices and interconnects shrink at the rate predicted by Moore’s law, gate density and design complexity on single integrated chip (IC) keep increasing in recent decades. The close to nanoscale fabrication process introduces more manufacturing errors. New failure mechanisms that are not covered by current fault models are observed in designs fabricated in new technologies and new materials. At the same time, the power and signal integrity issues that come with scaled supply voltages and higher operating frequencies increase the number of faults that violate the predefined timing margin. VLSI testing has become more and more important and challenging to verify the correctness of design and manufacturing processes. The diagram shown in Fig. 1.1 illustrates the simplified IC production flow. In the design phase, the test modules are inserted in the netlist and synthesized in the layout. Designers set timing margin carefully to account for the difference between simulation and actual operation mode, such as uncertainties introduced by process variation, temperature variation, clock jitter, etc. However, due to imperfect design and fabrication process, there are variations and defects that make the chip violate this timing margin and cause functional failure in field. Logic bugs, manufacturing error, and defective packaging process could be the source of errors.

Power Distribution Failure Analysis Using Transition-Delay Fault Patterns

Power distribution networks (PDNs) have been a vital part of modern designs. However, scaling technologies have increased the likelihood of defects in the PDN that may affect yield, escape, and reliability. Failure analysis is particularly difficult since there is no direct access to the PDN as there is to the design logic. We present a flow that generates transition-delay fault patterns to target open defects on the PDN. The flow identifies regions that could be susceptible to open defects and generates patterns that will exercise those regions to increase the likelihood of a timing failure should a defect exist in the PDN.