Sreejit Chakravarty

Techniques for minimizing power dissipation in scan and combinational circuits during test application

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.

A Study of Implication Based Pseudo Functional Testing

This paper presents a study of the implication based functional constraint extraction techniques to generate pseudo functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. Its impact on reducing the overkill in testing was analyzed, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, it was shown that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, the evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes

A scalable and efficient methodology to extract two node bridges from large industrial circuits

Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented.

Experimental evaluation of scan tests for bridges

An impressive body of theoretical research to model the behavior of bridges exists. We take that a step further and describe an experiment to compute single cycle scan tests for bridges and evaluate them in silicon. Experimental data, on a high volume part, shows that by marginally increasing the static bridge fault coverage of realistic bridges, unique parts missed by a comprehensive set of stuck-at tests were detected. We believe that this is the first silicon data on the value of adding single cycle scan tests for bridges to the manufacturing flow.

Fault models for speed failures caused by bridges and opens

A number of new transition fault models for resistive vias and contacts in static CMOS circuits that cause speed failures are presented. The uniqueness of the new fault models are formally established. Fault simulation experiments performed on a large microprocessor show that there is no correlation between the newly proposed models and the classical fault models. Finally, we show that failures caused by bridges and opens in domino CMOS circuits require different fault models, and different test application considerations, than static CMOS circuits. It shows that there are defects that do not cause errors when tests are applied at high speed but fail when tests are applied at slow speed. This contradicts an assumption often made in speed-binning.

A novel algorithm to extract two-node bridges

Defect based testing is based on the premise that it is possible to extract high probability defects viz. bridges and opens using layout and defect data. We present a very efficient algorithm to extract two-node bridges from layout. Comparison results with a popular tool show that our algorithm is considerably faster and that it has higher capacity.

An Approach to Minimizing Functional Constraints

Functional constraints are an integral part of the VLSI design methodology. Pseudo-functional scan ATPG and untestable fault identification are two areas in test where functional constraints are widely used. The number and complexity of these constraints for large designs become a limiting factor in their successful usage. In this paper the authors define a constraint minimization problem and present a powerful framework to simplify such constraints. The feasibility and effectiveness of this approach is demonstrated by using untestability analysis of large industrial benchmarks as a case study

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

This paper proposes novel algorithms for computing test patterns for transition faults in combinational circuits and fully scanned sequential circuits. The algorithms are based on the principle that s@ vectors can be effectively used to construct good quality transition test sets. Several algorithms are discussed. Experimental results obtained using the new algorithms show that there is a 20% reduction in test set size, test data volume and test application time compared to a state-of-the-art native transition test ATPG tool, without any reduction in fault coverage. Other benefits of our approach, viz. productivity improvement, constraint handling and design data compression are highlighted.

Locating bridging faults using dynamically computed stuck-at fault dictionaries

Novel algorithms for locating bridging faults, based on the voting and wired models, in combinational circuits are presented. The algorithm uses small portions of the stuck-at fault dictionary, not the bridge fault dictionary, computed during fault location. This, along with an implicit representation of bridging faults, contributes significantly to the efficiency of the algorithm. Experimental evaluation of the algorithm on ISCAS circuits is presented.

Transition tests for high performance microprocessors

The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.