Arun Gunda

Defect isolation using scan-path testing and electron beam probing in multi-level high density asics

Electron beam probing is a powerful technique for analyzing functional failures in integrated circuits. A common approach used for isolating defects is to trace a bad signal on a failing pin through the circuit. The inputs and outputs of each logical node can be compared against simulated results to determine functionality. This method has several limitations which are discussed in this paper -- most notably, it is often an extremely time consuming process. Scan- path designs have been introduced which increase the observability and controllability of internal circuit nodes. The use of ASIC scan-path architecture is increasing due to the improved testability compared to non-scan designs. Scan-path architecture also offers opportunities for more efficient failure analysis of functional failures. In this paper we present a successful method of defect isolation using scan-path testing in conjunction with electron beam probing. Using this method, a fault area or node is identified using a test datalog, and the defect is precisely located using an electron beam probe station. This paper discusses in detail the integration of scan testing with electron beam probing for isolating various defects on devices with multi-layer (3+) metallization, 500 K usable gates and 2000 scan elements.

Failure analysis for full-scan circuits

We present a complete system for failure analysis of full-scan circuits. A novel scheme has been proposed to handle multiple faults up to a certain extent by ranking the faults according to the likelihood of being present in the defective part. The user can interactively recompute the suspect fault list by changing some parameters. If the suspect fault list is large, we generate new test patterns to distinguish the faults in the suspect list. User can iterate over a defective part several times until the suspect fault list is reasonably small. Then each suspect site is probed using E-beam. This tool is integrated into design environment of LSI Logic Corporation and produced good results when applied on a few industry circuits.

Methods for improving transition delay fault coverage using broadside tests

Testing of delay faults require two pattern tests. Broadside and skewed-load testing are two approaches to test for delay faults in scan designs. The broadside approach is often preferred over the skewed-load approach in designs that also use the system clock for scan operations, since skewed-load requires a fast (at-speed) scan enable signal while broadside testing does not. In this paper, we propose new scan flip-flops to improve delay fault coverage for circuits with scan using broadside tests. The proposed flip-flops do not require a control signal to switch at-speed. This is a distinct advantage as the design effort required for timing closure of such control signals is significant. We also propose a circuit topology based flip-flop selection procedure that offers a scalable method for increasing the transition fault coverage. Experimental results on industrial circuits are included

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults

Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use an ATPG program for transition delay faults to generate test patterns for both faults. Experimental results are presented to evaluate the effectiveness of our approach

A novel method of improving transition delay fault coverage using multiple scan enable signals

We propose a novel delay test method for achieving higher delay fault coverage. Multiple scan enable signals are used none of which require the ability to switch at-speed between launch and capture cycles.

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets

Test Generation for Open Defects in CMOS Circuits

Open defects in CMOS circuits require two-pattern tests for detection. Traditionally, the only two-pattern tests included in manufacturing test are those targeting transition delay faults. Such tests, however, do not provide complete coverage of all the open defects. In this paper we propose the use of a unified test set that detects all inline resistance faults which model interconnect open defects and all transistor stuck-open faults which model intra-gate open defects in order to obtain a comprehensive coverage of open defects. We also describe a method of generating the proposed test set using an ATPG program for transition delay faults whose sizes are comparable to transition delay fault based test set

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions

We describe a novel method to partition flip-flops in scan chains into disjoint groups of flip-flops that are to be driven by independent scan enable signals to achieve higher delay fault coverage. The proposed method to partition flip-flops is motivated by our recent work which demonstrated that driving subsets of flip-flops by independent scan enable signals to launch signal transitions will lead to higher delay fault coverage by broadside tests. As in broadside test none of the scan enable signals need to switch at-speed. Experimental results for delay fault coverage improvement on larger ISCAS-89 benchmark and industrial circuits are presented

Accurate measurement of small delay defect coverage of test patterns

Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay defects by any given pattern set. We demonstrate that the proposed metric overcomes the identified shortcomings of previously published approaches. For several ISCAS and industrial circuits, we generate test patterns and compare their SDD coverage values using different methods. Experimental results also demonstrate that the proposed method is several times faster to compute. Finally, we evaluate different testing strategies for screening small delay defects.

Systematic Scan Reconfiguration

We present a new test data compression technique that achieves 10times to 40times compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain.