Juraj Marek

Fast 3-D Electrothermal Device/Circuit Simulation of Power Superjunction MOSFET Based on SDevice and HSPICE Interaction

Automated interaction of SDevice and HSPICE for fast 3-D electrothermal simulation based on the relaxation method is designed. The results are compared with device finite element model simulation and a direct method with an equivalent thermal 3-D RC network. The features and limitations of the methods are analyzed and presented. The designed electrothermal simulation based on the relaxation method is developed for Synopsys TCAD Sentaurus environment for decreasing the simulation time for complex 3-D devices. A power vertical superjunction MOSFET under an unclamped inductive switching test of device robustness is used to perform validation of the designed electrothermal simulation.

Advanced Methodology for Fast 3-D TCAD Device/Circuit Electrothermal Simulation and Analysis of Power HEMTs

This paper introduces an advanced methodology for fast 3-D Technology Computer Aided Design (TCAD) electrothermal simulation for the analysis of power devices. The proposed methodology is based on coupling finite element method (FEM) thermal and circuit electrical simulation in a mixed-mode setup. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. A new equivalent temperature-dependent nonlinear analytical large signal circuit model of HEMT is proposed. The model is implemented to Synopsys TCAD Sentaurus using compact model interface. The designed electrothermal simulation methodology is developed to shorten the simulation time for complex 3-D devices. This approach combines the speed and accuracy, and couples temperature nonuniformity to the active device electrothermal behavior. The simulation results are compared with the measured data and results of 2-D FEM simulations. The features and limitations of the methods are analyzed and presented.

Effective 3-D Device Electrothermal Simulation Analysis of Influence of Metallization Geometry on Multifinger Power HEMTs Properties

In this brief, obtained results of the electrothermal analysis of multifinger power high-electron mobility transistors (HEMTs) are presented. The analysis of thermal and electrical behavior is supported by effective 3-D electrothermal device simulation method developed for Synopsys TCAD Sentaurus environment using mixed-mode setup. The effects of multifinger HEMT structure metallization layout design are described and studied. Simulation results depict the significant effect of metallization geometry on the electrothermal properties and behavior of the power multifinger HEMTs.

Advanced methodology for fast 3-D TCAD electrothermal simulation of power HEMTs including package

This paper introduces an advanced methodology for fast 3-D TCAD electrothermal simulation for the analysis of complex power devices including package and cooling assemblies. The proposed methodology is based on coupling a 3-D finite element method (FEM) thermal model of the package, 3-D FEM electrical model of the metallization layers and circuit electrical model using a mixed-mode setup in Synopsys TCAD Sentaurus environment. This approach combines the speed and accuracy, and couples temperature and current density nonuniformity in structure and metallization layers. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. The simulation results are compared with measured data and 2/3-D FEM simulations. The low time consuming simulation approach helps to optimize more complex power structures and systems including all main fabrication parameters from semiconductor layers, metallization, package, and up to cooling assemblies.

Electro-thermal analysis and optimization of edge termination of power diode supported by 2D numerical modeling and simulation

Abstract High reliability and performance of power semiconductor devices depend on an optimized design based on a good understanding of their electro-thermal behavior and of the influence of parasitic components on their operation. This leads to the need for electro-thermal 2/3-D numerical modeling and simulation in power electronics as an efficient tool for analysis and optimization of device structure design and identification of critical regions. In this paper we present an analysis and geometry optimization of a high power pin diode structure supported by advanced 2-D mixed mode electro-thermal device and circuit simulation. Lowering of the operation temperature by better power management and heat dissipation due to an optimized structure design will allow withstanding higher current pulses and suppressing the damage of the analyzed structure by thermal breakdown.

Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

Abstract An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.

On-chip supply current monitoring units using magnetic force sensing

A built-in on-chip current sensors design based on magnetic force of is presented. The proposed sensors are aimed to be used for on-chip current testing in deep-submicron circuits with ultra low-voltage power supply. The advantage of the proposed monitors is mainly elimination of the undesired supply voltage reduction, commonly created by standard current test methods. Description of different sensor architectures, their designs and physical implementations on chip are presented. All the sensor versions were designed in 1.0 mum BiCMOS technology.

Analysis of Novel MagFET Structures for Built-in Current Sensors Supported by 3D Modeling and Simulation

Novel built-in current sensor structures based on selected electrophysical properties of a magnetic FET (MAGFET) is presented. The proposed sensor structures may be used for on-chip current testing in deep-submicron circuits with ultra low-voltage power supply. Their advantage is mainly in elimination of the undesired supply voltage reduction on the current monitor, commonly created by standard current test methods. Analysis of the influence of various device structures and dimensions on their electro-physical parameters and electrical characteristics is presented. All versions of MAGFET structure were designed using design rules of 1mum BiCMOS technology.

On-chip Integration of Magnetic Force Sensing Current Monitors

Novel built-in current sensor designs based on magnetic force of a magnetic FET (MAGFET) is presented. The proposed sensors are aimed to be used for on-chip current testing in deep-submicron circuits with ultra low-voltage power supply. The advantage of the proposed monitors is mainly elimination of the undesired supply voltage reduction, commonly created by standard current test methods. Description of two different sensor architectures, their designs and physical implementations on chip are presented. All the sensor versions were designed in 1.0 mum BiCMOS technology.

Post-deposition annealing and thermal stability of integrated self-aligned E/D-mode n ++ GaN/InAlN/AlN/GaN MOS HEMTs

We describe technology and evaluate thermal performance of enhancement/depletion (E/D)-mode n++GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate processing, where n++GaN layer was etched away only under the gate for E-mode and for D-mode stay intact. Gate contacts were isolated using a dielectric layer deposited at low temperature through an e-beam resist to retain the self-aligned approach. Threshold voltage of the as deposited E- and D-mode HEMTs was +0.6 V and -2.4 V, respectively. After post-deposition annealing (PDA) at 300 °C in N2 atmosphere the threshold voltage has been changed to +3 V and - 4,4 V for E- and D-mode HEMTs, respectively. These effects were explained by decreasing density of deep interface states in the D-mode HEMTs and decreasing surface donors at the semiconductor-oxide interface in case of the E-mode HEMTs. After PDA, electrical performance of both types of transistors was evaluated from room temperature to 150 °C. At elevated temperatures, injection and trapping of electrons from the gate metal to the oxide was found in D-mode HEMTs, while emission of electrons from the oxide-semiconductor interface states was crucial for the E-mode ones.