Ales Chvala

Fast 3-D Electrothermal Device/Circuit Simulation of Power Superjunction MOSFET Based on SDevice and HSPICE Interaction

Automated interaction of SDevice and HSPICE for fast 3-D electrothermal simulation based on the relaxation method is designed. The results are compared with device finite element model simulation and a direct method with an equivalent thermal 3-D RC network. The features and limitations of the methods are analyzed and presented. The designed electrothermal simulation based on the relaxation method is developed for Synopsys TCAD Sentaurus environment for decreasing the simulation time for complex 3-D devices. A power vertical superjunction MOSFET under an unclamped inductive switching test of device robustness is used to perform validation of the designed electrothermal simulation.

Advanced Methodology for Fast 3-D TCAD Device/Circuit Electrothermal Simulation and Analysis of Power HEMTs

This paper introduces an advanced methodology for fast 3-D Technology Computer Aided Design (TCAD) electrothermal simulation for the analysis of power devices. The proposed methodology is based on coupling finite element method (FEM) thermal and circuit electrical simulation in a mixed-mode setup. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. A new equivalent temperature-dependent nonlinear analytical large signal circuit model of HEMT is proposed. The model is implemented to Synopsys TCAD Sentaurus using compact model interface. The designed electrothermal simulation methodology is developed to shorten the simulation time for complex 3-D devices. This approach combines the speed and accuracy, and couples temperature nonuniformity to the active device electrothermal behavior. The simulation results are compared with the measured data and results of 2-D FEM simulations. The features and limitations of the methods are analyzed and presented.

Electrical Properties of Recessed Algan/Gan Schottky Diodes Under off–State Stress

Abstract Electrical properties of recessed and non-recessed AlGaN/GaN Schottky diodes under off-state stress were investigated. The samples were consecutively stressed by the stepped negative bias (−60 V). Before and after the stress I−V and C−V characteristics were evaluated to verify the device degradation process. Finally, the degradation mechanism and the influence of AlGaN recessed layer thickness on the electrical properties of the Schottky diodes were analysed. It was found that the short time stress influence on I−V characteristics was most negligible for the non-recessed sample. Shallow and deep recessed samples exhibited initial trap filling and reverse current decrease. Generally it was found that the stress voltage near 60 V caused recoverable device degradation

Gate leakage current in GaN-based mesa- and planar-type heterostructure field-effect transistors

Abstract The excessive gate leakage current of the planar- and mesa-type InAlN/GaN heterostructure field-effect transistors (HFETs) is evaluated. It is found that the gate current of the mesa-type HFETs is higher than that of the planar devices, particularly at low biases. Analyses of the gate current considering different transport mechanisms yielded identical thermionic currents (i.e., an identical Schottky barrier height) but a significantly higher leakage component in the mesa-type HFETs than in the planar devices. This additional current component observed in the mesa-type devices shows a nearly ohmic behavior. Mapping by the electron-beam induced current technique confirms an enhanced current located under the expanded gate contact and on the part of the mesa-sidewall, where the gate contact is placed. Two-dimensional simulation of the device structure shows that considerable part of the gate leakage current flows through the GaN buffer layer. These results underline the importance of a proper design of the device structure and layout (i.e., the use of planar structure with device insulation prepared by ion implantation rather than by mesa technique), and of the preparation of the GaN buffer (it should be semi-insulating) in order to fabricate reliable, low leakage current GaN-based HFETs.

Effective 3-D Device Electrothermal Simulation Analysis of Influence of Metallization Geometry on Multifinger Power HEMTs Properties

In this brief, obtained results of the electrothermal analysis of multifinger power high-electron mobility transistors (HEMTs) are presented. The analysis of thermal and electrical behavior is supported by effective 3-D electrothermal device simulation method developed for Synopsys TCAD Sentaurus environment using mixed-mode setup. The effects of multifinger HEMT structure metallization layout design are described and studied. Simulation results depict the significant effect of metallization geometry on the electrothermal properties and behavior of the power multifinger HEMTs.

Advanced methodology for fast 3-D TCAD electrothermal simulation of power HEMTs including package

This paper introduces an advanced methodology for fast 3-D TCAD electrothermal simulation for the analysis of complex power devices including package and cooling assemblies. The proposed methodology is based on coupling a 3-D finite element method (FEM) thermal model of the package, 3-D FEM electrical model of the metallization layers and circuit electrical model using a mixed-mode setup in Synopsys TCAD Sentaurus environment. This approach combines the speed and accuracy, and couples temperature and current density nonuniformity in structure and metallization layers. A power InAlN/GaN high-electron mobility transistor (HEMT) is used to perform validation of the designed electrothermal simulation. The simulation results are compared with measured data and 2/3-D FEM simulations. The low time consuming simulation approach helps to optimize more complex power structures and systems including all main fabrication parameters from semiconductor layers, metallization, package, and up to cooling assemblies.

Electro-thermal analysis and optimization of edge termination of power diode supported by 2D numerical modeling and simulation

Abstract High reliability and performance of power semiconductor devices depend on an optimized design based on a good understanding of their electro-thermal behavior and of the influence of parasitic components on their operation. This leads to the need for electro-thermal 2/3-D numerical modeling and simulation in power electronics as an efficient tool for analysis and optimization of device structure design and identification of critical regions. In this paper we present an analysis and geometry optimization of a high power pin diode structure supported by advanced 2-D mixed mode electro-thermal device and circuit simulation. Lowering of the operation temperature by better power management and heat dissipation due to an optimized structure design will allow withstanding higher current pulses and suppressing the damage of the analyzed structure by thermal breakdown.

Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

Abstract An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.

Post-deposition annealing and thermal stability of integrated self-aligned E/D-mode n ++ GaN/InAlN/AlN/GaN MOS HEMTs

We describe technology and evaluate thermal performance of enhancement/depletion (E/D)-mode n++GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate processing, where n++GaN layer was etched away only under the gate for E-mode and for D-mode stay intact. Gate contacts were isolated using a dielectric layer deposited at low temperature through an e-beam resist to retain the self-aligned approach. Threshold voltage of the as deposited E- and D-mode HEMTs was +0.6 V and -2.4 V, respectively. After post-deposition annealing (PDA) at 300 °C in N2 atmosphere the threshold voltage has been changed to +3 V and - 4,4 V for E- and D-mode HEMTs, respectively. These effects were explained by decreasing density of deep interface states in the D-mode HEMTs and decreasing surface donors at the semiconductor-oxide interface in case of the E-mode HEMTs. After PDA, electrical performance of both types of transistors was evaluated from room temperature to 150 °C. At elevated temperatures, injection and trapping of electrons from the gate metal to the oxide was found in D-mode HEMTs, while emission of electrons from the oxide-semiconductor interface states was crucial for the E-mode ones.

3-D device and circuit electrothermal simulations of power integrated circuit including package

In this paper we present an advanced methodology for effective 3-D device electrothermal simulation of power structures and power integrated circuits. The proposed electrothermal simulation is based on direct interconnection of a 3-D FEM thermal model and electrical circuit model of the device using a mixed-mode setup supported in Synopsys TCAD Sentaurus environment. This approach combines the speed and accuracy, and couples temperature nonuniformity to the active device electrothermal behaviour. The simulation results are compared with circuit electrothermal simulation which uses electrical RC network as an equivalent of the thermal system. The features and limitations of the methods are analyzed and presented.