Jürgen Koehl

Analysis, reduction and avoidance of crosstalk on VLSI chips

As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on-chip timing and even functionality. A method is presented to analyze crosstalk while taking into account timing relationship and timing criticality between coupling wires. The method is based upon the geometrical layout of the wires (adjacency), the signal slopes on the wires (circuit driving capability) and timing considerations. Based on these wire characteristics, a pattern driven routing tool imbeds the crosstalk critical nets in non-adjacent wiring tracks for crosstalk avoidance. The pattern driven routing capability may also be used for rerouting crosstalk critical nets of an already existing routing for crosstalk reduction. The crosstalk analysis and the routing tool described in this paper were used in three generations of VLSI processor chip designs for IBMs S/390 computers, always resulting in crosstalk-resistant hardware.

Yield Improvement by Local Wiring Redundancy

Technology migration from 130 nm to 90 nm has resulted in increased yield loss caused by opens in wiring interconnects and vias. Sensitivity to these defects can be significantly reduced through the use of design methodologies that use arbitrary networks with high degrees of redundancy instead of trees for signal wires. In this paper we describe a technique that improves yield by adding via redundancy through the use of local loops. The commonly used practice of inserting a second via adjacent to an existing via can only be applied to a limited number of vias, generates wrong-way wiring, and does not significantly reduce critical area because of the proximity of the two vias. Industry examples are cited to show that use of local loops to create redundancy reduces critical area, does not require wrong-way wiring, and achieves a higher percent of redundant vias. Addition of local loops does not impact timing or wireability of the design

DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit design

The concepts of design for manufacturability and design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now

IBM's 50 Million gate ASICs

circuit design, physical design and manufacturing process. New requirements like SoC, mixed analog/digital design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. For technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. Redesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to design individual blocks with high robustness (>6sigma). For abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. For the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices

Robust wiring networks for DfY considering timing constraints

There is no slowdown in the complexity increase for ASIC and SoC designs. As we write this paper in August, 2002, 40M gate ASICs are nearing tape-out, and 50M gate designs are likely to start before this conference takes place. This paper describes the current tool and methodology development efforts focused on enabling ASIC and SoC designs of these sizes and complexity, centered around the reduction of design turn-around-time, improvement of the quality of results and the modeling and optimization of deep sub-micron electrical effects.

Standard-cell-based design methodology for high-performance support chips

In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges in multiple loops can be removed the augmentation efficiency is further improved. As a special feature, our algorithm keeps timing constraints which have not been considered by previous GMRTA algorithms.

Mathematik im Chip-Design

We describe the methodology used for the design of a set of CMOS support chips used in the IBM S/390® Parallel Enterprise Server Generations 3 and 4. The logic design is based on functional units, and the majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. Custom library elements are used wherever needed for performance reasons. Using this approach, a density has been achieved that is comparable to those of contemporary custom designs, combined with very attractive turnaround times.

Mathematics of Chip Design

Chips sind die wohl komplexesten Strukturen, die vom Menschen entworfen und gefertigt wurden. Auf einem kleinen Silizium-Chip von der Grose eines Fingernagels werden heute Milliarden von Transistoren untergebracht, die mit vielen Millionen Verbindungen untereinander verknupft sind, wobei die Gesamtlange dieser Netze mehrere Kilometer betragen kann. Abb. 1 zeigt einen kleinen Ausschnitt (∼ 1 Milliardstel) eines Chips mit zweilagiger Verdrahtung im Raster-Tunnel-Mikroskop.

DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design

Chips are probably the most complex structures ever designed and produced by man. On a small silicon chip of the size of a fingernail, one is today able to accommodate billions of transistors, linked by millions of connecting wires whose total length can exceed several kilometres. Figure 1, which was made with a scanning tunnelling microscope, shows a very small part (about one billionth) of a modern chip with two wiring levels.